Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 4243d767d38694fcb5f967d69c36a1ec6bd7fb98 / . / include / bedbug / ppc.h
blob: 46bf8db1a74f972a22c689ef8502d8ba5b3bd09d [file] [log] [blame]
wdenk012771d2002-03-08 21:31:05 +0000[diff] [blame]1/* $Id$ */
2
3#ifndef _PPC_H
4#define _PPC_H
5
6/*======================================================================
7 *
8 * OPERANDS
9 *
10 *======================================================================*/
11
12enum OP_FIELD {
13 O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
14 O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
15 O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
16 O_cr2 };
17
18struct operand {
19 enum OP_FIELD field; /* The operand identifier from the
20 enum above */
21
22 char * name; /* Symbolic name of this operand */
23
24 unsigned int bits; /* The number of bits used by this
25 operand */
26
27 unsigned int shift; /* How far to the right the operand
28 should be shifted so that it is
29 aligned at the beginning of the
30 word */
31
32 unsigned int hint; /* A bitwise-inclusive-OR of the
33 values shown below. These are used
34 tell the disassembler how to print
35 this operand */
36};
37
38/* Values for operand hint */
39#define OH_SILENT 0x01 /* dont print this operand */
40#define OH_ADDR 0x02 /* this operand is an address */
41#define OH_REG 0x04 /* this operand is a register */
42#define OH_SPR 0x08 /* this operand is an SPR */
43#define OH_TBR 0x10 /* this operand is a TBR */
44#define OH_OFFSET 0x20 /* this operand is an offset */
45#define OH_LITERAL 0x40 /* a literal string */
46
47
48/*======================================================================
49 *
50 * OPCODES
51 *
52 *======================================================================*/
53
54/* From the MPCxxx instruction set documentation, all instructions are
55 * 32 bits long and word aligned. Bits 0-5 always specify the primary
56 * opcode. Many instructions also have an extended opcode.
57 */
58
59#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
60#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
61
62/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
63 * instruction forms
64 */
65
66
67/*-------------------------------------------------
68 * I-Form Instructions:
69 * bX
70 *-------------------------------------------------
71 * OPCD | LI |AA|LK
72 *-------------------------------------------------*/
73
74#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
75#define I_MASK I_OPCODE(0x3f,0x1,0x1)
76
77
78/*-------------------------------------------------
79 * B-Form Instructions:
80 * bcX
81 *-------------------------------------------------
82 * OPCD | BO | BI | BD |AA|LK
83 *-------------------------------------------------*/
84
85#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
86#define B_MASK B_OPCODE(0x3f,0x1,0x1)
87
88
89/*-------------------------------------------------
90 * SC-Form Instructions:
91 * sc
92 *-------------------------------------------------
93 * OPCD | 00000 | 00000 | 00000000000000 |1|0
94 *-------------------------------------------------*/
95
96#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
97#define SC_MASK SC_OPCODE(0x3f)
98
99
100/*-------------------------------------------------
101 * D-Form Instructions:
102 * addi addic addic. addis andi. andis. cmpi cmpli
103 * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
104 * ori oris stb stbu sth sthu stmw stw stwu subfic
105 * twi xori xoris
106 *-------------------------------------------------
107 * OPCD | D | A | d
108 * OPCD | D | A | SIMM
109 * OPCD | S | A | d
110 * OPCD | S | A | UIMM
111 * OPCD |crfD|0|L| A | SIMM
112 * OPCD |crfD|0|L| A | UIMM
113 * OPCD | TO | A | SIMM
114 *-------------------------------------------------*/
115
116#define D_OPCODE(i) MAKE_OPCODE(i)
117#define D_MASK MAKE_OPCODE(0x3f)
118
119
120/*-------------------------------------------------
121 * DS-Form Instructions:
122 * (none supported by MPC860)
123 *-------------------------------------------------
124 * OPCD | D | A | ds |XO
125 * OPCD | S | A | ds |XO
126 *-------------------------------------------------*/
127
128#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
129#define DS_MASK DS_OPCODE(0x3f,0x1)
130
131
132/*---------------------------------------------------
133 * X-Form Instructions:
134 * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
135 * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
136 * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
137 * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
138 * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
139 * orX orcX slwX srawX srawiX srwX stbux stbx
140 * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
141 * stwx sync tlbie tlbld tlbli tlbsync tw xorX
142 *---------------------------------------------------
143 * OPCD | D | A | B | XO |0
144 * OPCD | D | A | NB | XO |0
145 * OPCD | D | 00000 | B | XO |0
146 * OPCD | D | 00000 | 00000 | XO |0
147 * OPCD | D |0| SR | 00000 | XO |0
148 * OPCD | S | A | B | XO |Rc
149 * OPCD | S | A | B | XO |1
150 * OPCD | S | A | B | XO |0
151 * OPCD | S | A | NB | XO |0
152 * OPCD | S | A | 00000 | XO |Rc
153 * OPCD | S | 00000 | B | XO |0
154 * OPCD | S | 00000 | 00000 | XO |0
155 * OPCD | S |0| SR | 00000 | XO |0
156 * OPCD | S | A | SH | XO |Rc
157 * OPCD |crfD|0|L| A | SH | XO |0
158 * OPCD |crfD |00| A | B | XO |0
159 * OPCD |crfD |00|crfS |00| 00000 | XO |0
160 * OPCD |crfD |00| 00000 | 00000 | XO |0
161 * OPCD |crfD |00| 00000 | IMM |0| XO |Rc
162 * OPCD | TO | A | B | XO |0
163 * OPCD | D | 00000 | B | XO |Rc
164 * OPCD | D | 00000 | 00000 | XO |Rc
165 * OPCD | crbD | 00000 | 00000 | XO |Rc
166 * OPCD | 00000 | A | B | XO |0
167 * OPCD | 00000 | 00000 | B | XO |0
168 * OPCD | 00000 | 00000 | 00000 | XO |0
169 *---------------------------------------------------*/
170
171#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
172 ((rc) & 0x1))
173#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
174
175
176/*---------------------------------------------------
177 * XL-Form Instructions:
178 * bcctrX bclrX crand crandc creqv crnand crnor cror
179 * croc crxorisync mcrf rfi
180 *---------------------------------------------------
181 * OPCD | BO | BI | 00000 | XO |LK
182 * OPCD | crbD | crbA | crbB | XO |0
183 * OPCD |crfD |00|crfS |00| 00000 | XO |0
184 * OPCD | 00000 | 00000 | 00000 | XO |0
185 *---------------------------------------------------*/
186
187#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
188 ((lk) & 0x1))
189#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
190
191
192/*---------------------------------------------------
193 * XFX-Form Instructions:
194 * mfspr mftb mtcrf mtspr
195 *---------------------------------------------------
196 * OPCD | D | spr | XO |0
197 * OPCD | D |0| CRM |0| XO |0
198 * OPCD | S | spr | XO |0
199 * OPCD | D | tbr | XO |0
200 *---------------------------------------------------*/
201
202#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
203 ((rc) & 0x1))
204#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
205
206
207/*---------------------------------------------------
208 * XFL-Form Instructions:
209 * (none supported by MPC860)
210 *---------------------------------------------------
211 * OPCD |0| FM |0| B | XO |0
212 *---------------------------------------------------*/
213
214#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
215 ((rc) & 0x1))
216#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
217
218
219/*---------------------------------------------------
220 * XS-Form Instructions:
221 * (none supported by MPC860)
222 *---------------------------------------------------
223 * OPCD | S | A | sh | XO |sh|LK
224 *---------------------------------------------------*/
225
226#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
227 ((rc) & 0x1))
228#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
229
230
231/*---------------------------------------------------
232 * XO-Form Instructions:
233 * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
234 * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
235 * subfzeX
236 *---------------------------------------------------
237 * OPCD | D | A | B |OE| XO |Rc
238 * OPCD | D | A | B |0 | XO |Rc
239 * OPCD | D | A | 00000 |OE| XO |Rc
240 *---------------------------------------------------*/
241
242#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
243 (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
244#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
245
246
247/*---------------------------------------------------
248 * A-Form Instructions:
249 * (none supported by MPC860)
250 *---------------------------------------------------
251 * OPCD | D | A | B |00000| XO |Rc
252 * OPCD | D | A | B | C | XO |Rc
253 * OPCD | D | A | 00000 | C | XO |Rc
254 * OPCD | D | 00000 | B |00000| XO |Rc
255 *---------------------------------------------------*/
256
257#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
258 ((rc) & 0x1))
259#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
260
261
262/*---------------------------------------------------
263 * M-Form Instructions:
264 * rlwimiX rlwinmX rlwnmX
265 *---------------------------------------------------
266 * OPCD | S | A | SH | MB | ME |Rc
267 * OPCD | S | A | B | MB | ME |Rc
268 *---------------------------------------------------*/
269
270#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
271#define M_MASK M_OPCODE(0x3f,0x1)
272
273
274/*---------------------------------------------------
275 * MD-Form Instructions:
276 * (none supported by MPC860)
277 *---------------------------------------------------
278 * OPCD | S | A | sh | mb | XO |sh|Rc
279 * OPCD | S | A | sh | me | XO |sh|Rc
280 *---------------------------------------------------*/
281
282#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
283 ((rc) & 0x1))
284#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
285
286
287/*---------------------------------------------------
288 * MDS-Form Instructions:
289 * (none supported by MPC860)
290 *---------------------------------------------------
291 * OPCD | S | A | B | mb | XO |Rc
292 * OPCD | S | A | B | me | XO |Rc
293 *---------------------------------------------------*/
294
295#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
296 ((rc) & 0x1))
297#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
298
299#ifndef FALSE
300#define FALSE 0
301#define TRUE (!FALSE)
302#endif
303
304#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
305
306#define MAX_OPERANDS 8
307
308struct ppc_ctx;
309
310struct opcode {
311 unsigned long opcode; /* The complete opcode as produced by
312 one of the XXX_OPCODE macros above */
313
314 unsigned long mask; /* The mask to use on an instruction
315 before comparing with the opcode
316 field to see if it matches */
317
318 enum OP_FIELD fields[MAX_OPERANDS];
319 /* An array defining the operands for
320 this opcode. The values of the
321 array are the operand identifiers */
322
323 int (*hfunc)(struct ppc_ctx *);
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]324 /* Address of a function to handle the given
wdenk012771d2002-03-08 21:31:05 +0000[diff] [blame]325 mnemonic */
326
327 char * name; /* The symbolic name of this opcode */
328
329 unsigned int hint; /* A bitwise-inclusive-OR of the
330 values shown below. These are used
331 tell the disassembler how to print
332 some operands for this opcode */
333};
334
335/* values for opcode hints */
336#define H_RELATIVE 0x1 /* The address operand is relative */
337#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */
338#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */
339
340struct ppc_ctx {
341 struct opcode * op;
342 unsigned long instr;
343 unsigned int flags;
344 int datalen;
345 char data[ 256 ];
346 char radix_fmt[ 8 ];
347 unsigned char * virtual;
348};
349
350
351/*======================================================================
352 *
353 * FUNCTIONS
354 *
355 *======================================================================*/
356
357/* Values for flags as passed to various ppc routines */
358#define F_RADOCTAL 0x1 /* output radix = unsigned octal */
359#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */
360#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */
361#define F_RADHEX 0x8 /* output radix = unsigned hex */
362#define F_SIMPLE 0x10 /* use simplified mnemonics */
363#define F_SYMBOL 0x20 /* use symbol lookups for addresses */
364#define F_INSTR 0x40 /* output the raw instruction */
365#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory
366 rather than from the HMI */
367#define F_LINENO 0x100 /* show line number info if available */
368#define F_VALIDONLY 0x200 /* cache: valid entries only */
369
370/* Values for assembler error codes */
371#define E_ASM_BAD_OPCODE 1
372#define E_ASM_NUM_OPERANDS 2
373#define E_ASM_BAD_REGISTER 3
374#define E_ASM_BAD_SPR 4
375#define E_ASM_BAD_TBR 5
376
377extern int disppc __P((unsigned char *,unsigned char *,int,
378 int (*)(const char *), unsigned long));
379extern int print_source_line __P((char *,char *,int,
380 int (*pfunc)(const char *)));
381extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
382extern int handle_bc __P((struct ppc_ctx *));
383extern unsigned long asmppc __P((unsigned long,char*,int*));
384extern char *asm_error_str __P((int));
385
386/*======================================================================
387 *
388 * GLOBAL VARIABLES
389 *
390 *======================================================================*/
391
392extern struct operand operands[];
393extern const unsigned int n_operands;
394extern struct opcode opcodes[];
395extern const unsigned int n_opcodes;
396
397#endif /* _PPC_H */
398
399
400/*
401 * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
402 * All rights reserved.
403 *
404 * Redistribution and use in source and binary forms are freely
405 * permitted provided that the above copyright notice and this
406 * paragraph and the following disclaimer are duplicated in all
407 * such forms.
408 *
409 * This software is provided "AS IS" and without any express or
410 * implied warranties, including, without limitation, the implied
411 * warranties of merchantability and fitness for a particular
412 * purpose.
413 */