Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 - 2015 Xilinx, Inc. |
| 4 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_HARDWARE_H |
| 8 | #define _ASM_ARCH_HARDWARE_H |
| 9 | |
Siva Durga Prasad Paladugu | 055792a | 2015-03-03 15:01:44 +0530 | [diff] [blame] | 10 | #define ZYNQ_I2C_BASEADDR0 0xFF020000 |
| 11 | #define ZYNQ_I2C_BASEADDR1 0xFF030000 |
| 12 | |
Siva Durga Prasad Paladugu | 937ad76 | 2015-11-17 14:30:09 +0530 | [diff] [blame] | 13 | #define ARASAN_NAND_BASEADDR 0xFF100000 |
| 14 | |
Siva Durga Prasad Paladugu | 4628c50 | 2017-07-13 19:01:11 +0530 | [diff] [blame] | 15 | #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 |
| 16 | #define ZYNQMP_TCM_SIZE 0x40000 |
| 17 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 18 | #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 |
| 19 | #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 |
Michal Simek | 3eb32de | 2016-08-15 09:41:36 +0200 | [diff] [blame] | 20 | #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 |
| 21 | #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 |
| 22 | |
| 23 | #define PS_MODE0 BIT(0) |
| 24 | #define PS_MODE1 BIT(1) |
| 25 | #define PS_MODE2 BIT(2) |
| 26 | #define PS_MODE3 BIT(3) |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 27 | |
Michal Simek | 29b9b71 | 2018-05-17 14:06:06 +0200 | [diff] [blame] | 28 | #define RESET_REASON_DEBUG_SYS BIT(6) |
| 29 | #define RESET_REASON_SOFT BIT(5) |
| 30 | #define RESET_REASON_SRST BIT(4) |
| 31 | #define RESET_REASON_PSONLY BIT(3) |
| 32 | #define RESET_REASON_PMU BIT(2) |
| 33 | #define RESET_REASON_INTERNAL BIT(1) |
| 34 | #define RESET_REASON_EXTERNAL BIT(0) |
| 35 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 36 | struct crlapb_regs { |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 37 | u32 reserved0[36]; |
| 38 | u32 cpu_r5_ctrl; /* 0x90 */ |
| 39 | u32 reserved1[37]; |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 40 | u32 timestamp_ref_ctrl; /* 0x128 */ |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 41 | u32 reserved2[53]; |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 42 | u32 boot_mode; /* 0x200 */ |
Michal Simek | 29b9b71 | 2018-05-17 14:06:06 +0200 | [diff] [blame] | 43 | u32 reserved3_0[7]; |
| 44 | u32 reset_reason; /* 0x220 */ |
| 45 | u32 reserved3_1[6]; |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 46 | u32 rst_lpd_top; /* 0x23C */ |
Michal Simek | 3eb32de | 2016-08-15 09:41:36 +0200 | [diff] [blame] | 47 | u32 reserved4[4]; |
| 48 | u32 boot_pin_ctrl; /* 0x250 */ |
| 49 | u32 reserved5[21]; |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) |
| 53 | |
Michal Simek | c23d3f8 | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 54 | #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 55 | #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 |
| 56 | #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 |
| 57 | |
Michal Simek | c23d3f8 | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 58 | struct iou_scntr_secure { |
| 59 | u32 counter_control_register; |
| 60 | u32 reserved0[7]; |
| 61 | u32 base_frequency_id_register; |
| 62 | }; |
| 63 | |
| 64 | #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) |
| 65 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 66 | /* Bootmode setting values */ |
| 67 | #define BOOT_MODES_MASK 0x0000000F |
Siva Durga Prasad Paladugu | 30f0fc7 | 2015-03-13 11:10:26 +0530 | [diff] [blame] | 68 | #define QSPI_MODE_24BIT 0x00000001 |
| 69 | #define QSPI_MODE_32BIT 0x00000002 |
Michal Simek | 108e184 | 2015-10-05 10:51:12 +0200 | [diff] [blame] | 70 | #define SD_MODE 0x00000003 /* sd 0 */ |
| 71 | #define SD_MODE1 0x00000005 /* sd 1 */ |
Siva Durga Prasad Paladugu | 30f0fc7 | 2015-03-13 11:10:26 +0530 | [diff] [blame] | 72 | #define NAND_MODE 0x00000004 |
Michal Simek | 02d66cd | 2015-04-15 15:02:28 +0200 | [diff] [blame] | 73 | #define EMMC_MODE 0x00000006 |
Michal Simek | 203a944 | 2016-04-29 13:00:10 +0200 | [diff] [blame] | 74 | #define USB_MODE 0x00000007 |
Siva Durga Prasad Paladugu | 29a77d2 | 2016-09-21 11:45:05 +0530 | [diff] [blame] | 75 | #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 76 | #define JTAG_MODE 0x00000000 |
Michal Simek | 94ddcaa | 2016-08-30 16:17:27 +0200 | [diff] [blame] | 77 | #define BOOT_MODE_USE_ALT 0x100 |
| 78 | #define BOOT_MODE_ALT_SHIFT 12 |
Michal Simek | 2740d37 | 2016-10-26 09:24:32 +0200 | [diff] [blame] | 79 | /* SW secondary boot modes 0xa - 0xd */ |
| 80 | #define SW_USBHOST_MODE 0x0000000A |
| 81 | #define SW_SATA_MODE 0x0000000B |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 82 | |
Michal Simek | f2e373f | 2015-07-22 09:27:11 +0200 | [diff] [blame] | 83 | #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 |
| 84 | |
| 85 | struct iou_slcr_regs { |
| 86 | u32 mio_pin[78]; |
| 87 | u32 reserved[442]; |
| 88 | }; |
| 89 | |
| 90 | #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) |
| 91 | |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 92 | #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 |
| 93 | |
| 94 | struct rpu_regs { |
| 95 | u32 rpu_glbl_ctrl; |
| 96 | u32 reserved0[63]; |
| 97 | u32 rpu0_cfg; /* 0x100 */ |
| 98 | u32 reserved1[63]; |
| 99 | u32 rpu1_cfg; /* 0x200 */ |
| 100 | }; |
| 101 | |
| 102 | #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) |
| 103 | |
| 104 | #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 |
| 105 | |
| 106 | struct crfapb_regs { |
| 107 | u32 reserved0[65]; |
| 108 | u32 rst_fpd_apu; /* 0x104 */ |
| 109 | u32 reserved1; |
| 110 | }; |
| 111 | |
| 112 | #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) |
| 113 | |
| 114 | #define ZYNQMP_APU_BASEADDR 0xFD5C0000 |
| 115 | |
| 116 | struct apu_regs { |
| 117 | u32 reserved0[16]; |
| 118 | u32 rvbar_addr0_l; /* 0x40 */ |
| 119 | u32 rvbar_addr0_h; /* 0x44 */ |
| 120 | u32 reserved1[20]; |
| 121 | }; |
| 122 | |
| 123 | #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) |
| 124 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 125 | /* Board version value */ |
Michal Simek | c23d3f8 | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 126 | #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 127 | #define ZYNQMP_CSU_VERSION_SILICON 0x0 |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 128 | #define ZYNQMP_CSU_VERSION_QEMU 0x3 |
| 129 | |
Michal Simek | 50d8cef | 2017-08-22 14:58:53 +0200 | [diff] [blame] | 130 | #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 |
| 131 | |
Michal Simek | c23d3f8 | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 132 | #define ZYNQMP_SILICON_VER_MASK 0xF000 |
| 133 | #define ZYNQMP_SILICON_VER_SHIFT 12 |
| 134 | |
| 135 | struct csu_regs { |
| 136 | u32 reserved0[17]; |
| 137 | u32 version; |
| 138 | }; |
| 139 | |
| 140 | #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) |
| 141 | |
Michal Simek | 456e454 | 2017-01-09 10:05:16 +0100 | [diff] [blame] | 142 | #define ZYNQMP_PMU_BASEADDR 0xFFD80000 |
| 143 | |
| 144 | struct pmu_regs { |
| 145 | u32 reserved[18]; |
| 146 | u32 gen_storage6; /* 0x48 */ |
| 147 | }; |
| 148 | |
| 149 | #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) |
| 150 | |
Siva Durga Prasad Paladugu | 8d52653 | 2017-07-25 11:51:37 +0530 | [diff] [blame] | 151 | #define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 |
| 152 | #define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 |
| 153 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 154 | #endif /* _ASM_ARCH_HARDWARE_H */ |