Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 2 | /* |
Ye Li | 325cd01 | 2020-05-03 22:19:52 +0800 | [diff] [blame] | 3 | * Copyright 2017-2019 NXP |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 4 | * |
| 5 | * Peng Fan <peng.fan@nxp.com> |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 9 | #include <cpu_func.h> |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 10 | #include <asm/arch/imx-regs.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/clock.h> |
| 13 | #include <asm/arch/sys_proto.h> |
| 14 | #include <asm/mach-imx/hab.h> |
| 15 | #include <asm/mach-imx/boot_mode.h> |
| 16 | #include <asm/mach-imx/syscounter.h> |
| 17 | #include <asm/armv8/mmu.h> |
Peng Fan | c98e032 | 2019-08-27 06:25:58 +0000 | [diff] [blame] | 18 | #include <dm/uclass.h> |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 19 | #include <errno.h> |
| 20 | #include <fdt_support.h> |
| 21 | #include <fsl_wdog.h> |
| 22 | #include <imx_sip.h> |
| 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
Stefano Babic | f8b509b | 2019-09-20 08:47:53 +0200 | [diff] [blame] | 26 | #if defined(CONFIG_IMX_HAB) |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 27 | struct imx_sec_config_fuse_t const imx_sec_config_fuse = { |
| 28 | .bank = 1, |
| 29 | .word = 3, |
| 30 | }; |
| 31 | #endif |
| 32 | |
| 33 | int timer_init(void) |
| 34 | { |
| 35 | #ifdef CONFIG_SPL_BUILD |
| 36 | struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; |
| 37 | unsigned long freq = readl(&sctr->cntfid0); |
| 38 | |
| 39 | /* Update with accurate clock frequency */ |
| 40 | asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); |
| 41 | |
| 42 | clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, |
| 43 | SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); |
| 44 | #endif |
| 45 | |
| 46 | gd->arch.tbl = 0; |
| 47 | gd->arch.tbu = 0; |
| 48 | |
| 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | void enable_tzc380(void) |
| 53 | { |
| 54 | struct iomuxc_gpr_base_regs *gpr = |
| 55 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 56 | |
| 57 | /* Enable TZASC and lock setting */ |
| 58 | setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); |
| 59 | setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); |
Peng Fan | c0e47fc | 2019-12-27 10:19:42 +0800 | [diff] [blame] | 60 | if (is_imx8mm() || is_imx8mn() || is_imx8mp()) |
Peng Fan | 99047fc | 2019-08-27 06:25:30 +0000 | [diff] [blame] | 61 | setbits_le32(&gpr->gpr[10], BIT(1)); |
Ye Li | 4c97c46 | 2019-08-27 06:25:34 +0000 | [diff] [blame] | 62 | /* |
| 63 | * set Region 0 attribute to allow secure and non-secure |
| 64 | * read/write permission. Found some masters like usb dwc3 |
| 65 | * controllers can't work with secure memory. |
| 66 | */ |
| 67 | writel(0xf0000000, TZASC_BASE_ADDR + 0x108); |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | void set_wdog_reset(struct wdog_regs *wdog) |
| 71 | { |
| 72 | /* |
| 73 | * Output WDOG_B signal to reset external pmic or POR_B decided by |
| 74 | * the board design. Without external reset, the peripherals/DDR/ |
| 75 | * PMIC are not reset, that may cause system working abnormal. |
| 76 | * WDZST bit is write-once only bit. Align this bit in kernel, |
| 77 | * otherwise kernel code will have no chance to set this bit. |
| 78 | */ |
| 79 | setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); |
| 80 | } |
| 81 | |
| 82 | static struct mm_region imx8m_mem_map[] = { |
| 83 | { |
| 84 | /* ROM */ |
| 85 | .virt = 0x0UL, |
| 86 | .phys = 0x0UL, |
| 87 | .size = 0x100000UL, |
| 88 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 89 | PTE_BLOCK_OUTER_SHARE |
| 90 | }, { |
Gary Bisson | 5c72a45 | 2018-11-14 17:55:28 +0100 | [diff] [blame] | 91 | /* CAAM */ |
| 92 | .virt = 0x100000UL, |
| 93 | .phys = 0x100000UL, |
| 94 | .size = 0x8000UL, |
| 95 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 96 | PTE_BLOCK_NON_SHARE | |
| 97 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 98 | }, { |
| 99 | /* TCM */ |
| 100 | .virt = 0x7C0000UL, |
| 101 | .phys = 0x7C0000UL, |
| 102 | .size = 0x80000UL, |
| 103 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 104 | PTE_BLOCK_NON_SHARE | |
| 105 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 106 | }, { |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 107 | /* OCRAM */ |
| 108 | .virt = 0x900000UL, |
| 109 | .phys = 0x900000UL, |
| 110 | .size = 0x200000UL, |
| 111 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 112 | PTE_BLOCK_OUTER_SHARE |
| 113 | }, { |
| 114 | /* AIPS */ |
| 115 | .virt = 0xB00000UL, |
| 116 | .phys = 0xB00000UL, |
| 117 | .size = 0x3f500000UL, |
| 118 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 119 | PTE_BLOCK_NON_SHARE | |
| 120 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 121 | }, { |
| 122 | /* DRAM1 */ |
| 123 | .virt = 0x40000000UL, |
| 124 | .phys = 0x40000000UL, |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 125 | .size = PHYS_SDRAM_SIZE, |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 126 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 127 | PTE_BLOCK_OUTER_SHARE |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 128 | #ifdef PHYS_SDRAM_2_SIZE |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 129 | }, { |
| 130 | /* DRAM2 */ |
| 131 | .virt = 0x100000000UL, |
| 132 | .phys = 0x100000000UL, |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 133 | .size = PHYS_SDRAM_2_SIZE, |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 134 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 135 | PTE_BLOCK_OUTER_SHARE |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 136 | #endif |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 137 | }, { |
| 138 | /* List terminator */ |
| 139 | 0, |
| 140 | } |
| 141 | }; |
| 142 | |
| 143 | struct mm_region *mem_map = imx8m_mem_map; |
| 144 | |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 145 | void enable_caches(void) |
| 146 | { |
| 147 | /* |
| 148 | * If OPTEE runs, remove OPTEE memory from MMU table to |
| 149 | * avoid speculative prefetch. OPTEE runs at the top of |
| 150 | * the first memory bank |
| 151 | */ |
| 152 | if (rom_pointer[1]) |
| 153 | imx8m_mem_map[5].size -= rom_pointer[1]; |
| 154 | |
| 155 | icache_enable(); |
| 156 | dcache_enable(); |
| 157 | } |
| 158 | |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 159 | static u32 get_cpu_variant_type(u32 type) |
| 160 | { |
| 161 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 162 | struct fuse_bank *bank = &ocotp->bank[1]; |
| 163 | struct fuse_bank1_regs *fuse = |
| 164 | (struct fuse_bank1_regs *)bank->fuse_regs; |
| 165 | |
| 166 | u32 value = readl(&fuse->tester4); |
| 167 | |
Peng Fan | 6781508 | 2020-02-05 17:34:54 +0800 | [diff] [blame] | 168 | if (type == MXC_CPU_IMX8MQ) { |
| 169 | if ((value & 0x3) == 0x2) |
| 170 | return MXC_CPU_IMX8MD; |
| 171 | else if (value & 0x200000) |
| 172 | return MXC_CPU_IMX8MQL; |
| 173 | |
| 174 | } else if (type == MXC_CPU_IMX8MM) { |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 175 | switch (value & 0x3) { |
| 176 | case 2: |
| 177 | if (value & 0x1c0000) |
| 178 | return MXC_CPU_IMX8MMDL; |
| 179 | else |
| 180 | return MXC_CPU_IMX8MMD; |
| 181 | case 3: |
| 182 | if (value & 0x1c0000) |
| 183 | return MXC_CPU_IMX8MMSL; |
| 184 | else |
| 185 | return MXC_CPU_IMX8MMS; |
| 186 | default: |
| 187 | if (value & 0x1c0000) |
| 188 | return MXC_CPU_IMX8MML; |
| 189 | break; |
| 190 | } |
Peng Fan | 1a07d91 | 2020-02-05 17:39:27 +0800 | [diff] [blame] | 191 | } else if (type == MXC_CPU_IMX8MN) { |
| 192 | switch (value & 0x3) { |
| 193 | case 2: |
| 194 | if (value & 0x1000000) |
| 195 | return MXC_CPU_IMX8MNDL; |
| 196 | else |
| 197 | return MXC_CPU_IMX8MND; |
| 198 | case 3: |
| 199 | if (value & 0x1000000) |
| 200 | return MXC_CPU_IMX8MNSL; |
| 201 | else |
| 202 | return MXC_CPU_IMX8MNS; |
| 203 | default: |
| 204 | if (value & 0x1000000) |
| 205 | return MXC_CPU_IMX8MNL; |
| 206 | break; |
| 207 | } |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | return type; |
| 211 | } |
| 212 | |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 213 | u32 get_cpu_rev(void) |
| 214 | { |
| 215 | struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; |
| 216 | u32 reg = readl(&ana_pll->digprog); |
| 217 | u32 type = (reg >> 16) & 0xff; |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 218 | u32 major_low = (reg >> 8) & 0xff; |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 219 | u32 rom_version; |
| 220 | |
| 221 | reg &= 0xff; |
| 222 | |
Peng Fan | 69cec07 | 2019-12-27 10:14:02 +0800 | [diff] [blame] | 223 | /* iMX8MP */ |
| 224 | if (major_low == 0x43) { |
| 225 | return (MXC_CPU_IMX8MP << 12) | reg; |
| 226 | } else if (major_low == 0x42) { |
| 227 | /* iMX8MN */ |
Peng Fan | 1a07d91 | 2020-02-05 17:39:27 +0800 | [diff] [blame] | 228 | type = get_cpu_variant_type(MXC_CPU_IMX8MN); |
Peng Fan | 5d2f206 | 2019-06-27 17:23:49 +0800 | [diff] [blame] | 229 | } else if (major_low == 0x41) { |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 230 | type = get_cpu_variant_type(MXC_CPU_IMX8MM); |
| 231 | } else { |
| 232 | if (reg == CHIP_REV_1_0) { |
| 233 | /* |
Peng Fan | c23fbdd | 2019-10-16 10:24:17 +0000 | [diff] [blame] | 234 | * For B0 chip, the DIGPROG is not updated, |
| 235 | * it is still TO1.0. we have to check ROM |
| 236 | * version or OCOTP_READ_FUSE_DATA. |
| 237 | * 0xff0055aa is magic number for B1. |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 238 | */ |
Peng Fan | c23fbdd | 2019-10-16 10:24:17 +0000 | [diff] [blame] | 239 | if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) { |
| 240 | reg = CHIP_REV_2_1; |
| 241 | } else { |
| 242 | rom_version = |
| 243 | readl((void __iomem *)ROM_VERSION_A0); |
| 244 | if (rom_version != CHIP_REV_1_0) { |
| 245 | rom_version = readl((void __iomem *)ROM_VERSION_B0); |
Patrick Wildt | d4a78b9 | 2019-11-19 09:42:06 +0100 | [diff] [blame] | 246 | rom_version &= 0xff; |
Peng Fan | c23fbdd | 2019-10-16 10:24:17 +0000 | [diff] [blame] | 247 | if (rom_version == CHIP_REV_2_0) |
| 248 | reg = CHIP_REV_2_0; |
| 249 | } |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 250 | } |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 251 | } |
Peng Fan | 6781508 | 2020-02-05 17:34:54 +0800 | [diff] [blame] | 252 | |
| 253 | type = get_cpu_variant_type(type); |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | return (type << 12) | reg; |
| 257 | } |
| 258 | |
| 259 | static void imx_set_wdog_powerdown(bool enable) |
| 260 | { |
| 261 | struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 262 | struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; |
| 263 | struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; |
| 264 | |
| 265 | /* Write to the PDE (Power Down Enable) bit */ |
| 266 | writew(enable, &wdog1->wmcr); |
| 267 | writew(enable, &wdog2->wmcr); |
| 268 | writew(enable, &wdog3->wmcr); |
| 269 | } |
| 270 | |
Peng Fan | c98e032 | 2019-08-27 06:25:58 +0000 | [diff] [blame] | 271 | int arch_cpu_init_dm(void) |
| 272 | { |
| 273 | struct udevice *dev; |
| 274 | int ret; |
| 275 | |
Peng Fan | 3c07334 | 2019-10-16 03:01:51 +0000 | [diff] [blame] | 276 | if (CONFIG_IS_ENABLED(CLK)) { |
| 277 | ret = uclass_get_device_by_name(UCLASS_CLK, |
| 278 | "clock-controller@30380000", |
| 279 | &dev); |
| 280 | if (ret < 0) { |
| 281 | printf("Failed to find clock node. Check device tree\n"); |
| 282 | return ret; |
| 283 | } |
Peng Fan | c98e032 | 2019-08-27 06:25:58 +0000 | [diff] [blame] | 284 | } |
| 285 | |
| 286 | return 0; |
| 287 | } |
| 288 | |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 289 | int arch_cpu_init(void) |
| 290 | { |
Peng Fan | c0b30d7 | 2019-04-17 09:41:16 +0000 | [diff] [blame] | 291 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 292 | /* |
Peng Fan | d0ca289 | 2019-08-27 06:25:37 +0000 | [diff] [blame] | 293 | * ROM might disable clock for SCTR, |
| 294 | * enable the clock before timer_init. |
| 295 | */ |
| 296 | if (IS_ENABLED(CONFIG_SPL_BUILD)) |
| 297 | clock_enable(CCGR_SCTR, 1); |
| 298 | /* |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 299 | * Init timer at very early state, because sscg pll setting |
| 300 | * will use it |
| 301 | */ |
| 302 | timer_init(); |
| 303 | |
| 304 | if (IS_ENABLED(CONFIG_SPL_BUILD)) { |
| 305 | clock_init(); |
| 306 | imx_set_wdog_powerdown(false); |
| 307 | } |
| 308 | |
Peng Fan | c0b30d7 | 2019-04-17 09:41:16 +0000 | [diff] [blame] | 309 | if (is_imx8mq()) { |
| 310 | clock_enable(CCGR_OCOTP, 1); |
| 311 | if (readl(&ocotp->ctrl) & 0x200) |
| 312 | writel(0x200, &ocotp->ctrl_clr); |
| 313 | } |
| 314 | |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 315 | return 0; |
| 316 | } |
| 317 | |
Peng Fan | c9823b0 | 2019-09-16 03:09:36 +0000 | [diff] [blame] | 318 | #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) |
| 319 | struct rom_api *g_rom_api = (struct rom_api *)0x980; |
| 320 | |
| 321 | enum boot_device get_boot_device(void) |
| 322 | { |
| 323 | volatile gd_t *pgd = gd; |
| 324 | int ret; |
| 325 | u32 boot; |
| 326 | u16 boot_type; |
| 327 | u8 boot_instance; |
| 328 | enum boot_device boot_dev = SD1_BOOT; |
| 329 | |
| 330 | ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, |
| 331 | ((uintptr_t)&boot) ^ QUERY_BT_DEV); |
| 332 | gd = pgd; |
| 333 | |
| 334 | if (ret != ROM_API_OKAY) { |
| 335 | puts("ROMAPI: failure at query_boot_info\n"); |
| 336 | return -1; |
| 337 | } |
| 338 | |
| 339 | boot_type = boot >> 16; |
| 340 | boot_instance = (boot >> 8) & 0xff; |
| 341 | |
| 342 | switch (boot_type) { |
| 343 | case BT_DEV_TYPE_SD: |
| 344 | boot_dev = boot_instance + SD1_BOOT; |
| 345 | break; |
| 346 | case BT_DEV_TYPE_MMC: |
| 347 | boot_dev = boot_instance + MMC1_BOOT; |
| 348 | break; |
| 349 | case BT_DEV_TYPE_NAND: |
| 350 | boot_dev = NAND_BOOT; |
| 351 | break; |
| 352 | case BT_DEV_TYPE_FLEXSPINOR: |
| 353 | boot_dev = QSPI_BOOT; |
| 354 | break; |
| 355 | case BT_DEV_TYPE_USB: |
| 356 | boot_dev = USB_BOOT; |
| 357 | break; |
| 358 | default: |
| 359 | break; |
| 360 | } |
| 361 | |
| 362 | return boot_dev; |
| 363 | } |
| 364 | #endif |
| 365 | |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 366 | bool is_usb_boot(void) |
| 367 | { |
| 368 | return get_boot_device() == USB_BOOT; |
| 369 | } |
| 370 | |
| 371 | #ifdef CONFIG_OF_SYSTEM_SETUP |
| 372 | int ft_system_setup(void *blob, bd_t *bd) |
| 373 | { |
| 374 | int i = 0; |
| 375 | int rc; |
| 376 | int nodeoff; |
| 377 | |
| 378 | /* Disable the CPU idle for A0 chip since the HW does not support it */ |
| 379 | if (is_soc_rev(CHIP_REV_1_0)) { |
| 380 | static const char * const nodes_path[] = { |
| 381 | "/cpus/cpu@0", |
| 382 | "/cpus/cpu@1", |
| 383 | "/cpus/cpu@2", |
| 384 | "/cpus/cpu@3", |
| 385 | }; |
| 386 | |
| 387 | for (i = 0; i < ARRAY_SIZE(nodes_path); i++) { |
| 388 | nodeoff = fdt_path_offset(blob, nodes_path[i]); |
| 389 | if (nodeoff < 0) |
| 390 | continue; /* Not found, skip it */ |
| 391 | |
Marek Vasut | e2e7a77 | 2020-04-24 21:37:33 +0200 | [diff] [blame] | 392 | debug("Found %s node\n", nodes_path[i]); |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 393 | |
| 394 | rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); |
Marek Vasut | e2e7a77 | 2020-04-24 21:37:33 +0200 | [diff] [blame] | 395 | if (rc == -FDT_ERR_NOTFOUND) |
| 396 | continue; |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 397 | if (rc) { |
| 398 | printf("Unable to update property %s:%s, err=%s\n", |
| 399 | nodes_path[i], "status", fdt_strerror(rc)); |
| 400 | return rc; |
| 401 | } |
| 402 | |
Marek Vasut | e2e7a77 | 2020-04-24 21:37:33 +0200 | [diff] [blame] | 403 | debug("Remove %s:%s\n", nodes_path[i], |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 404 | "cpu-idle-states"); |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | return 0; |
| 409 | } |
| 410 | #endif |
| 411 | |
Marek Vasut | 64dc4de | 2020-04-29 15:04:21 +0200 | [diff] [blame] | 412 | #if !CONFIG_IS_ENABLED(SYSRESET) |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 413 | void reset_cpu(ulong addr) |
| 414 | { |
Claudius Heine | e73f394 | 2020-04-29 15:04:23 +0200 | [diff] [blame] | 415 | struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 416 | |
Ye Li | 54a915a | 2019-12-09 00:47:18 -0800 | [diff] [blame] | 417 | /* Clear WDA to trigger WDOG_B immediately */ |
| 418 | writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr); |
Peng Fan | 24290d9 | 2019-08-27 06:25:41 +0000 | [diff] [blame] | 419 | |
Ye Li | 54a915a | 2019-12-09 00:47:18 -0800 | [diff] [blame] | 420 | while (1) { |
| 421 | /* |
Harald Seiler | ec0c447 | 2020-04-29 15:04:22 +0200 | [diff] [blame] | 422 | * spin for .5 seconds before reset |
Ye Li | 54a915a | 2019-12-09 00:47:18 -0800 | [diff] [blame] | 423 | */ |
| 424 | } |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 425 | } |
Peng Fan | 24290d9 | 2019-08-27 06:25:41 +0000 | [diff] [blame] | 426 | #endif |
Peng Fan | 5760d8d | 2020-04-22 10:51:13 +0800 | [diff] [blame] | 427 | |
| 428 | #if defined(CONFIG_ARCH_MISC_INIT) |
| 429 | static void acquire_buildinfo(void) |
| 430 | { |
| 431 | u64 atf_commit = 0; |
| 432 | |
| 433 | /* Get ARM Trusted Firmware commit id */ |
| 434 | atf_commit = call_imx_sip(IMX_SIP_BUILDINFO, |
| 435 | IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); |
| 436 | if (atf_commit == 0xffffffff) { |
| 437 | debug("ATF does not support build info\n"); |
| 438 | atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */ |
| 439 | } |
| 440 | |
| 441 | printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit); |
| 442 | } |
| 443 | |
| 444 | int arch_misc_init(void) |
| 445 | { |
| 446 | acquire_buildinfo(); |
| 447 | |
| 448 | return 0; |
| 449 | } |
| 450 | #endif |
Ye Li | 325cd01 | 2020-05-03 22:19:52 +0800 | [diff] [blame] | 451 | |
| 452 | void imx_tmu_arch_init(void *reg_base) |
| 453 | { |
Ye Li | a00f2f0 | 2020-05-03 22:19:53 +0800 | [diff] [blame^] | 454 | if (is_imx8mm() || is_imx8mn()) { |
Ye Li | 325cd01 | 2020-05-03 22:19:52 +0800 | [diff] [blame] | 455 | /* Load TCALIV and TASR from fuses */ |
| 456 | struct ocotp_regs *ocotp = |
| 457 | (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 458 | struct fuse_bank *bank = &ocotp->bank[3]; |
| 459 | struct fuse_bank3_regs *fuse = |
| 460 | (struct fuse_bank3_regs *)bank->fuse_regs; |
| 461 | |
| 462 | u32 tca_rt, tca_hr, tca_en; |
| 463 | u32 buf_vref, buf_slope; |
| 464 | |
| 465 | tca_rt = fuse->ana0 & 0xFF; |
| 466 | tca_hr = (fuse->ana0 & 0xFF00) >> 8; |
| 467 | tca_en = (fuse->ana0 & 0x2000000) >> 25; |
| 468 | |
| 469 | buf_vref = (fuse->ana0 & 0x1F00000) >> 20; |
| 470 | buf_slope = (fuse->ana0 & 0xF0000) >> 16; |
| 471 | |
| 472 | writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); |
| 473 | writel((tca_en << 31) | (tca_hr << 16) | tca_rt, |
| 474 | (ulong)reg_base + 0x30); |
| 475 | } |
| 476 | } |