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git01.mediatek.com / filogic / uboot / 419228a4e585000722d3822cae0f3f0d72cdd12d / . / board / zeus / update.c
blob: ac738ef2ab3c3804edaa465a24f244a02e48d233 [file] [log] [blame]
Stefan Roesea5d182e2007-08-14 14:44:41 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesea5d182e2007-08-14 14:44:41 +0200[diff] [blame]6 */
7
8#include <config.h>
9#include <common.h>
10#include <command.h>
11#include <asm/processor.h>
12#include <asm/io.h>
Stefan Roesede21eab2010-09-16 14:30:37 +0200[diff] [blame]13#include <asm/ppc4xx-gpio.h>
Stefan Roesea5d182e2007-08-14 14:44:41 +0200[diff] [blame]14#include <i2c.h>
15
16#if defined(CONFIG_ZEUS)
17
18u8 buf_zeus_ce[] = {
19/*00 01 02 03 04 05 06 07 */
20 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
21/*08 09 0a 0b 0c 0d 0e 0f */
22 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
23/*10 11 12 13 14 15 16 17 */
24 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
25/*18 19 1a 1b 1c 1d 1e 1f */
26 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
27
28u8 buf_zeus_pe[] = {
29
30/* CPU_CLOCK_DIV 1 = 00
31 CPU_PLB_FREQ_DIV 3 = 10
32 OPB_PLB_FREQ_DIV 2 = 01
33 EBC_PLB_FREQ_DIV 2 = 00
34 MAL_PLB_FREQ_DIV 1 = 00
35 PCI_PLB_FRQ_DIV 3 = 10
36 PLL_PLLOUTA = IS SET
37 PLL_OPERATING = IS NOT SET
38 PLL_FDB_MUL 10 = 1010
39 PLL_FWD_DIV_A 3 = 101
40 PLL_FWD_DIV_B 3 = 101
41 TUNE = 0x2be */
42/*00 01 02 03 04 05 06 07 */
43 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
44/*08 09 0a 0b 0c 0d 0e 0f */
45 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
46/*10 11 12 13 14 15 16 17 */
47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
48/*18 19 1a 1b 1c 1d 1e 1f */
49 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
50
51static int update_boot_eeprom(void)
52{
53 u32 len = 0x20;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]54 u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR;
Stefan Roesea5d182e2007-08-14 14:44:41 +0200[diff] [blame]55 u8 *pbuf;
56 u8 base;
57 int i;
58
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]59 if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) {
Stefan Roesea5d182e2007-08-14 14:44:41 +0200[diff] [blame]60 pbuf = buf_zeus_pe;
61 base = 0x40;
62 } else {
63 pbuf = buf_zeus_ce;
64 base = 0x00;
65 }
66
67 for (i = 0; i < len; i++, base++) {
68 if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
69 printf("i2c_write fail\n");
70 return 1;
71 }
72 udelay(11000);
73 }
74
75 return 0;
76}
77
Wolfgang Denk6262d0212010-06-28 22:00:46 +0200[diff] [blame]78int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
Stefan Roesea5d182e2007-08-14 14:44:41 +0200[diff] [blame]79{
80 return update_boot_eeprom();
81}
82
83U_BOOT_CMD (
84 update_boot_eeprom, 1, 1, do_update_boot_eeprom,
Peter Tyserdfb72b82009-01-27 18:03:12 -0600[diff] [blame]85 "update boot eeprom content",
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200[diff] [blame]86 ""
Stefan Roesea5d182e2007-08-14 14:44:41 +0200[diff] [blame]87);
88
89#endif