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git01.mediatek.com / filogic / uboot / 415ef9b466ee16527de609306ddbce7e6ed1ad8c / . / arch / arm / dts / sun50i-h616.dtsi
blob: 953e8fac20f05782c3cf303ccd6a1c66a019ff1f [file] [log] [blame]
Jernej Skrabec415ef9b2021-01-11 21:11:50 +0100[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2020 Arm Ltd.
3// based on the H6 dtsi, which is:
4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/sun50i-h616-ccu.h>
8#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9#include <dt-bindings/reset/sun50i-h616-ccu.h>
10#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
11
12/ {
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 compatible = "arm,cortex-a53";
23 device_type = "cpu";
24 reg = <0>;
25 enable-method = "psci";
26 clocks = <&ccu CLK_CPUX>;
27 };
28
29 cpu1: cpu@1 {
30 compatible = "arm,cortex-a53";
31 device_type = "cpu";
32 reg = <1>;
33 enable-method = "psci";
34 clocks = <&ccu CLK_CPUX>;
35 };
36
37 cpu2: cpu@2 {
38 compatible = "arm,cortex-a53";
39 device_type = "cpu";
40 reg = <2>;
41 enable-method = "psci";
42 clocks = <&ccu CLK_CPUX>;
43 };
44
45 cpu3: cpu@3 {
46 compatible = "arm,cortex-a53";
47 device_type = "cpu";
48 reg = <3>;
49 enable-method = "psci";
50 clocks = <&ccu CLK_CPUX>;
51 };
52 };
53
54 reserved-memory {
55 #address-cells = <2>;
56 #size-cells = <2>;
57 ranges;
58
59 /* 512KiB reserved for ARM Trusted Firmware (BL31) */
60 secmon_reserved: secmon@40000000 {
61 reg = <0x0 0x40000000 0x0 0x80000>;
62 no-map;
63 };
64 };
65
66 osc24M: osc24M_clk {
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <24000000>;
70 clock-output-names = "osc24M";
71 };
72
73 pmu {
74 compatible = "arm,cortex-a53-pmu";
75 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
80 };
81
82 psci {
83 compatible = "arm,psci-0.2";
84 method = "smc";
85 };
86
87 timer {
88 compatible = "arm,armv8-timer";
89 arm,no-tick-in-suspend;
90 interrupts = <GIC_PPI 13
91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
92 <GIC_PPI 14
93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
94 <GIC_PPI 11
95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
96 <GIC_PPI 10
97 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
98 };
99
100 soc {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0x0 0x0 0x0 0x40000000>;
105
106 syscon: syscon@3000000 {
107 compatible = "allwinner,sun50i-h616-system-control";
108 reg = <0x03000000 0x1000>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112
113 sram_c: sram@28000 {
114 compatible = "mmio-sram";
115 reg = <0x00028000 0x30000>;
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges = <0 0x00028000 0x30000>;
119 };
120 };
121
122 ccu: clock@3001000 {
123 compatible = "allwinner,sun50i-h616-ccu";
124 reg = <0x03001000 0x1000>;
125 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
126 clock-names = "hosc", "losc", "iosc";
127 #clock-cells = <1>;
128 #reset-cells = <1>;
129 };
130
131 watchdog: watchdog@30090a0 {
132 compatible = "allwinner,sun50i-h616-wdt",
133 "allwinner,sun6i-a31-wdt";
134 reg = <0x030090a0 0x20>;
135 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&osc24M>;
137 status = "disabled";
138 };
139
140 pio: pinctrl@300b000 {
141 compatible = "allwinner,sun50i-h616-pinctrl";
142 reg = <0x0300b000 0x400>;
143 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
152 clock-names = "apb", "hosc", "losc";
153 gpio-controller;
154 #gpio-cells = <3>;
155 interrupt-controller;
156 #interrupt-cells = <3>;
157
158 ext_rgmii_pins: rgmii-pins {
159 pins = "PI0", "PI1", "PI2", "PI3", "PI4",
160 "PI5", "PI7", "PI8", "PI9", "PI10",
161 "PI11", "PI12", "PI13", "PI14", "PI15",
162 "PI16";
163 function = "emac0";
164 drive-strength = <40>;
165 };
166
167 i2c0_pins: i2c0-pins {
168 pins = "PI6", "PI7";
169 function = "i2c0";
170 };
171
172 i2c3_ph_pins: i2c3-ph-pins {
173 pins = "PH4", "PH5";
174 function = "i2c3";
175 };
176
177 ir_rx_pin: ir_rx_pin {
178 pins = "PH10";
179 function = "ir_rx";
180 };
181
182 mmc0_pins: mmc0-pins {
183 pins = "PF0", "PF1", "PF2", "PF3",
184 "PF4", "PF5";
185 function = "mmc0";
186 drive-strength = <30>;
187 bias-pull-up;
188 };
189
190 mmc1_pins: mmc1-pins {
191 pins = "PG0", "PG1", "PG2", "PG3",
192 "PG4", "PG5";
193 function = "mmc1";
194 drive-strength = <30>;
195 bias-pull-up;
196 };
197
198 mmc2_pins: mmc2-pins {
199 pins = "PC0", "PC1", "PC5", "PC6",
200 "PC8", "PC9", "PC10", "PC11",
201 "PC13", "PC14", "PC15", "PC16";
202 function = "mmc2";
203 drive-strength = <30>;
204 bias-pull-up;
205 };
206
207 spi0_pins: spi0-pins {
208 pins = "PC0", "PC2", "PC3", "PC4";
209 function = "spi0";
210 };
211
212 spi1_pins: spi1-pins {
213 pins = "PH6", "PH7", "PH8";
214 function = "spi1";
215 };
216
217 spi1_cs_pin: spi1-cs-pin {
218 pins = "PH5";
219 function = "spi1";
220 };
221
222 uart0_ph_pins: uart0-ph-pins {
223 pins = "PH0", "PH1";
224 function = "uart0";
225 };
226
227 uart1_pins: uart1-pins {
228 pins = "PG6", "PG7";
229 function = "uart1";
230 };
231
232 uart1_rts_cts_pins: uart1-rts-cts-pins {
233 pins = "PG8", "PG9";
234 function = "uart1";
235 };
236 };
237
238 gic: interrupt-controller@3021000 {
239 compatible = "arm,gic-400";
240 reg = <0x03021000 0x1000>,
241 <0x03022000 0x2000>,
242 <0x03024000 0x2000>,
243 <0x03026000 0x2000>;
244 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
245 interrupt-controller;
246 #interrupt-cells = <3>;
247 };
248
249 mmc0: mmc@4020000 {
250 compatible = "allwinner,sun50i-h616-mmc",
251 "allwinner,sun50i-a100-mmc";
252 reg = <0x04020000 0x1000>;
253 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
254 clock-names = "ahb", "mmc";
255 resets = <&ccu RST_BUS_MMC0>;
256 reset-names = "ahb";
257 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&mmc0_pins>;
260 status = "disabled";
261 cap-sd-highspeed;
262 cap-mmc-highspeed;
263 mmc-ddr-3_3v;
264 mmc-ddr-1_8v;
265 cap-sdio-irq;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 };
269
270 mmc1: mmc@4021000 {
271 compatible = "allwinner,sun50i-h616-mmc",
272 "allwinner,sun50i-a100-mmc";
273 reg = <0x04021000 0x1000>;
274 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
275 clock-names = "ahb", "mmc";
276 resets = <&ccu RST_BUS_MMC1>;
277 reset-names = "ahb";
278 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&mmc1_pins>;
281 status = "disabled";
282 cap-sd-highspeed;
283 cap-mmc-highspeed;
284 mmc-ddr-3_3v;
285 mmc-ddr-1_8v;
286 cap-sdio-irq;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 };
290
291 mmc2: mmc@4022000 {
292 compatible = "allwinner,sun50i-h616-emmc",
293 "allwinner,sun50i-a100-emmc";
294 reg = <0x04022000 0x1000>;
295 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
296 clock-names = "ahb", "mmc";
297 resets = <&ccu RST_BUS_MMC2>;
298 reset-names = "ahb";
299 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&mmc2_pins>;
302 status = "disabled";
303 cap-sd-highspeed;
304 cap-mmc-highspeed;
305 mmc-ddr-3_3v;
306 mmc-ddr-1_8v;
307 cap-sdio-irq;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
311
312 uart0: serial@5000000 {
313 compatible = "snps,dw-apb-uart";
314 reg = <0x05000000 0x400>;
315 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
316 reg-shift = <2>;
317 reg-io-width = <4>;
318 clocks = <&ccu CLK_BUS_UART0>;
319 resets = <&ccu RST_BUS_UART0>;
320 status = "disabled";
321 };
322
323 uart1: serial@5000400 {
324 compatible = "snps,dw-apb-uart";
325 reg = <0x05000400 0x400>;
326 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
327 reg-shift = <2>;
328 reg-io-width = <4>;
329 clocks = <&ccu CLK_BUS_UART1>;
330 resets = <&ccu RST_BUS_UART1>;
331 status = "disabled";
332 };
333
334 uart2: serial@5000800 {
335 compatible = "snps,dw-apb-uart";
336 reg = <0x05000800 0x400>;
337 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
338 reg-shift = <2>;
339 reg-io-width = <4>;
340 clocks = <&ccu CLK_BUS_UART2>;
341 resets = <&ccu RST_BUS_UART2>;
342 status = "disabled";
343 };
344
345 uart3: serial@5000c00 {
346 compatible = "snps,dw-apb-uart";
347 reg = <0x05000c00 0x400>;
348 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
349 reg-shift = <2>;
350 reg-io-width = <4>;
351 clocks = <&ccu CLK_BUS_UART3>;
352 resets = <&ccu RST_BUS_UART3>;
353 status = "disabled";
354 };
355
356 uart4: serial@5001000 {
357 compatible = "snps,dw-apb-uart";
358 reg = <0x05001000 0x400>;
359 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
360 reg-shift = <2>;
361 reg-io-width = <4>;
362 clocks = <&ccu CLK_BUS_UART4>;
363 resets = <&ccu RST_BUS_UART4>;
364 status = "disabled";
365 };
366
367 uart5: serial@5001400 {
368 compatible = "snps,dw-apb-uart";
369 reg = <0x05001400 0x400>;
370 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
371 reg-shift = <2>;
372 reg-io-width = <4>;
373 clocks = <&ccu CLK_BUS_UART5>;
374 resets = <&ccu RST_BUS_UART5>;
375 status = "disabled";
376 };
377
378 i2c0: i2c@5002000 {
379 compatible = "allwinner,sun50i-h616-i2c",
380 "allwinner,sun6i-a31-i2c";
381 reg = <0x05002000 0x400>;
382 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&ccu CLK_BUS_I2C0>;
384 resets = <&ccu RST_BUS_I2C0>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c0_pins>;
387 status = "disabled";
388 #address-cells = <1>;
389 #size-cells = <0>;
390 };
391
392 i2c1: i2c@5002400 {
393 compatible = "allwinner,sun50i-h616-i2c",
394 "allwinner,sun6i-a31-i2c";
395 reg = <0x05002400 0x400>;
396 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&ccu CLK_BUS_I2C1>;
398 resets = <&ccu RST_BUS_I2C1>;
399 status = "disabled";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 };
403
404 i2c2: i2c@5002800 {
405 compatible = "allwinner,sun50i-h616-i2c",
406 "allwinner,sun6i-a31-i2c";
407 reg = <0x05002800 0x400>;
408 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&ccu CLK_BUS_I2C2>;
410 resets = <&ccu RST_BUS_I2C2>;
411 status = "disabled";
412 #address-cells = <1>;
413 #size-cells = <0>;
414 };
415
416 i2c3: i2c@5002c00 {
417 compatible = "allwinner,sun50i-h616-i2c",
418 "allwinner,sun6i-a31-i2c";
419 reg = <0x05002c00 0x400>;
420 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&ccu CLK_BUS_I2C3>;
422 resets = <&ccu RST_BUS_I2C3>;
423 status = "disabled";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 };
427
428 i2c4: i2c@5003000 {
429 compatible = "allwinner,sun50i-h616-i2c",
430 "allwinner,sun6i-a31-i2c";
431 reg = <0x05003000 0x400>;
432 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&ccu CLK_BUS_I2C4>;
434 resets = <&ccu RST_BUS_I2C4>;
435 status = "disabled";
436 #address-cells = <1>;
437 #size-cells = <0>;
438 };
439
440 spi0: spi@5010000 {
441 compatible = "allwinner,sun50i-h616-spi",
442 "allwinner,sun8i-h3-spi";
443 reg = <0x05010000 0x1000>;
444 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
446 clock-names = "ahb", "mod";
447 resets = <&ccu RST_BUS_SPI0>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&spi0_pins>;
450 status = "disabled";
451 #address-cells = <1>;
452 #size-cells = <0>;
453 };
454
455 spi1: spi@5011000 {
456 compatible = "allwinner,sun50i-h616-spi",
457 "allwinner,sun8i-h3-spi";
458 reg = <0x05011000 0x1000>;
459 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
461 clock-names = "ahb", "mod";
462 resets = <&ccu RST_BUS_SPI1>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&spi1_pins>;
465 status = "disabled";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 };
469
470 emac0: ethernet@5020000 {
471 compatible = "allwinner,sun50i-h616-emac",
472 "allwinner,sun50i-a64-emac";
473 syscon = <&syscon>;
474 reg = <0x05020000 0x10000>;
475 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "macirq";
477 resets = <&ccu RST_BUS_EMAC0>;
478 reset-names = "stmmaceth";
479 clocks = <&ccu CLK_BUS_EMAC0>;
480 clock-names = "stmmaceth";
481 status = "disabled";
482
483 mdio0: mdio {
484 compatible = "snps,dwmac-mdio";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 };
488 };
489
490 emac1: ethernet@5030000 {
491 compatible = "allwinner,sun50i-h616-emac";
492 syscon = <&syscon 1>;
493 reg = <0x05030000 0x10000>;
494 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
495 interrupt-names = "macirq";
496 resets = <&ccu RST_BUS_EMAC1>;
497 reset-names = "stmmaceth";
498 clocks = <&ccu CLK_BUS_EMAC1>;
499 clock-names = "stmmaceth";
500 status = "disabled";
501
502 mdio1: mdio {
503 compatible = "snps,dwmac-mdio";
504 #address-cells = <1>;
505 #size-cells = <0>;
506 };
507 };
508
509 usbotg: usb@5100000 {
510 compatible = "allwinner,sun50i-h616-musb",
511 "allwinner,sun8i-h3-musb";
512 reg = <0x05100000 0x0400>;
513 clocks = <&ccu CLK_BUS_OTG>;
514 resets = <&ccu RST_BUS_OTG>;
515 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-names = "mc";
517 phys = <&usbphy 0>;
518 phy-names = "usb";
519 extcon = <&usbphy 0>;
520 status = "disabled";
521 };
522
523 usbphy: phy@5100400 {
524 compatible = "allwinner,sun50i-h616-usb-phy";
525 reg = <0x05100400 0x24>,
526 <0x05101800 0x14>,
527 <0x05200800 0x14>,
528 <0x05310800 0x14>,
529 <0x05311800 0x14>;
530 reg-names = "phy_ctrl",
531 "pmu0",
532 "pmu1",
533 "pmu2",
534 "pmu3";
535 clocks = <&ccu CLK_USB_PHY0>,
536 <&ccu CLK_USB_PHY1>,
537 <&ccu CLK_USB_PHY2>,
538 <&ccu CLK_USB_PHY3>;
539 clock-names = "usb0_phy",
540 "usb1_phy",
541 "usb2_phy",
542 "usb3_phy";
543 resets = <&ccu RST_USB_PHY0>,
544 <&ccu RST_USB_PHY1>,
545 <&ccu RST_USB_PHY2>,
546 <&ccu RST_USB_PHY3>;
547 reset-names = "usb0_reset",
548 "usb1_reset",
549 "usb2_reset",
550 "usb3_reset";
551 status = "disabled";
552 #phy-cells = <1>;
553 };
554
555 ehci0: usb@5101000 {
556 compatible = "allwinner,sun50i-h616-ehci",
557 "generic-ehci";
558 reg = <0x05101000 0x100>;
559 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&ccu CLK_BUS_OHCI0>,
561 <&ccu CLK_BUS_EHCI0>,
562 <&ccu CLK_USB_OHCI0>;
563 resets = <&ccu RST_BUS_OHCI0>,
564 <&ccu RST_BUS_EHCI0>;
565 phys = <&usbphy 0>;
566 phy-names = "usb";
567 status = "disabled";
568 };
569
570 ohci0: usb@5101400 {
571 compatible = "allwinner,sun50i-h616-ohci",
572 "generic-ohci";
573 reg = <0x05101400 0x100>;
574 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&ccu CLK_BUS_OHCI0>,
576 <&ccu CLK_USB_OHCI0>;
577 resets = <&ccu RST_BUS_OHCI0>;
578 phys = <&usbphy 0>;
579 phy-names = "usb";
580 status = "disabled";
581 };
582
583 ehci1: usb@5200000 {
584 compatible = "allwinner,sun50i-h616-ehci",
585 "generic-ehci";
586 reg = <0x05200000 0x100>;
587 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&ccu CLK_BUS_OHCI1>,
589 <&ccu CLK_BUS_EHCI1>,
590 <&ccu CLK_USB_OHCI1>;
591 resets = <&ccu RST_BUS_OHCI1>,
592 <&ccu RST_BUS_EHCI1>;
593 phys = <&usbphy 1>;
594 phy-names = "usb";
595 status = "disabled";
596 };
597
598 ohci1: usb@5200400 {
599 compatible = "allwinner,sun50i-h616-ohci",
600 "generic-ohci";
601 reg = <0x05200400 0x100>;
602 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&ccu CLK_BUS_OHCI1>,
604 <&ccu CLK_USB_OHCI1>;
605 resets = <&ccu RST_BUS_OHCI1>;
606 phys = <&usbphy 1>;
607 phy-names = "usb";
608 status = "disabled";
609 };
610
611 ehci2: usb@5310000 {
612 compatible = "allwinner,sun50i-h616-ehci",
613 "generic-ehci";
614 reg = <0x05310000 0x100>;
615 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&ccu CLK_BUS_OHCI2>,
617 <&ccu CLK_BUS_EHCI2>,
618 <&ccu CLK_USB_OHCI2>;
619 resets = <&ccu RST_BUS_OHCI2>,
620 <&ccu RST_BUS_EHCI2>;
621 phys = <&usbphy 2>;
622 phy-names = "usb";
623 status = "disabled";
624 };
625
626 ohci2: usb@5310400 {
627 compatible = "allwinner,sun50i-h616-ohci",
628 "generic-ohci";
629 reg = <0x05310400 0x100>;
630 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&ccu CLK_BUS_OHCI2>,
632 <&ccu CLK_USB_OHCI2>;
633 resets = <&ccu RST_BUS_OHCI2>;
634 phys = <&usbphy 2>;
635 phy-names = "usb";
636 status = "disabled";
637 };
638
639 ehci3: usb@5311000 {
640 compatible = "allwinner,sun50i-h616-ehci",
641 "generic-ehci";
642 reg = <0x05311000 0x100>;
643 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&ccu CLK_BUS_OHCI3>,
645 <&ccu CLK_BUS_EHCI3>,
646 <&ccu CLK_USB_OHCI3>;
647 resets = <&ccu RST_BUS_OHCI3>,
648 <&ccu RST_BUS_EHCI3>;
649 phys = <&usbphy 3>;
650 phy-names = "usb";
651 status = "disabled";
652 };
653
654 ohci3: usb@5311400 {
655 compatible = "allwinner,sun50i-h616-ohci",
656 "generic-ohci";
657 reg = <0x05311400 0x100>;
658 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&ccu CLK_BUS_OHCI3>,
660 <&ccu CLK_USB_OHCI3>;
661 resets = <&ccu RST_BUS_OHCI3>;
662 phys = <&usbphy 3>;
663 phy-names = "usb";
664 status = "disabled";
665 };
666
667 rtc: rtc@7000000 {
668 compatible = "allwinner,sun50i-h616-rtc",
669 "allwinner,sun50i-h6-rtc";
670 reg = <0x07000000 0x400>;
671 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
673 clock-output-names = "osc32k", "osc32k-out", "iosc";
674 #clock-cells = <1>;
675 };
676
677 r_ccu: clock@7010000 {
678 compatible = "allwinner,sun50i-h616-r-ccu";
679 reg = <0x07010000 0x400>;
680 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
681 <&ccu CLK_PLL_PERIPH0>;
682 clock-names = "hosc", "losc", "iosc", "pll-periph";
683 #clock-cells = <1>;
684 #reset-cells = <1>;
685 };
686
687 r_pio: pinctrl@7022000 {
688 compatible = "allwinner,sun50i-h616-r-pinctrl";
689 reg = <0x07022000 0x400>;
690 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
692 clock-names = "apb", "hosc", "losc";
693 gpio-controller;
694 #gpio-cells = <3>;
695 interrupt-controller;
696 #interrupt-cells = <3>;
697
698 r_i2c_pins: r-i2c-pins {
699 pins = "PL0", "PL1";
700 function = "s_i2c";
701 };
702
703 r_rsb_pins: r-rsb-pins {
704 pins = "PL0", "PL1";
705 function = "s_rsb";
706 };
707 };
708
709 ir: ir@7040000 {
710 compatible = "allwinner,sun50i-h616-ir",
711 "allwinner,sun6i-a31-ir";
712 reg = <0x07040000 0x400>;
713 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&r_ccu CLK_R_APB1_IR>,
715 <&r_ccu CLK_IR>;
716 clock-names = "apb", "ir";
717 resets = <&r_ccu RST_R_APB1_IR>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&ir_rx_pin>;
720 status = "disabled";
721 };
722
723 r_i2c: i2c@7081400 {
724 compatible = "allwinner,sun50i-h616-i2c",
725 "allwinner,sun6i-a31-i2c";
726 reg = <0x07081400 0x400>;
727 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&r_ccu CLK_R_APB2_I2C>;
729 resets = <&r_ccu RST_R_APB2_I2C>;
730 status = "disabled";
731 #address-cells = <1>;
732 #size-cells = <0>;
733 };
734
735 r_rsb: rsb@7083000 {
736 compatible = "allwinner,sun50i-h616-rsb",
737 "allwinner,sun8i-a23-rsb";
738 reg = <0x07083000 0x400>;
739 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&r_ccu CLK_R_APB2_RSB>;
741 clock-frequency = <3000000>;
742 resets = <&r_ccu RST_R_APB2_RSB>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&r_rsb_pins>;
745 status = "disabled";
746 #address-cells = <1>;
747 #size-cells = <0>;
748 };
749 };
750};