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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
David Brownell45064002009-05-15 23:47:12 +02002/*
3 * Copyright (C) 2004 Texas Instruments.
4 * Copyright (C) 2009 David Brownell
David Brownell45064002009-05-15 23:47:12 +02005 */
6
Tom Rinia4312892024-04-30 07:35:53 -06007#include <config.h>
Tom Rini8c70baa2021-12-14 13:36:40 -05008#include <clock_legacy.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
David Brownell45064002009-05-15 23:47:12 +020010#include <asm/arch/hardware.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Tom Rinia4312892024-04-30 07:35:53 -060012#include <asm/u-boot.h>
Sekhar Nori302fc2f2009-11-12 11:07:22 -050013#include <asm/io.h>
David Brownell45064002009-05-15 23:47:12 +020014
Hadli, Manjunath0dfccbe2012-02-06 00:30:44 +000015DECLARE_GLOBAL_DATA_PTR;
16
David Brownell45064002009-05-15 23:47:12 +020017/* offsets from PLL controller base */
18#define PLLC_PLLCTL 0x100
19#define PLLC_PLLM 0x110
20#define PLLC_PREDIV 0x114
21#define PLLC_PLLDIV1 0x118
22#define PLLC_PLLDIV2 0x11c
23#define PLLC_PLLDIV3 0x120
24#define PLLC_POSTDIV 0x128
25#define PLLC_BPDIV 0x12c
26#define PLLC_PLLDIV4 0x160
27#define PLLC_PLLDIV5 0x164
28#define PLLC_PLLDIV6 0x168
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040029#define PLLC_PLLDIV7 0x16c
David Brownell45064002009-05-15 23:47:12 +020030#define PLLC_PLLDIV8 0x170
31#define PLLC_PLLDIV9 0x174
32
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040033unsigned int sysdiv[9] = {
34 PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
35 PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
Sekhar Nori302fc2f2009-11-12 11:07:22 -050036};
37
38int clk_get(enum davinci_clk_ids id)
39{
40 int pre_div;
41 int pllm;
42 int post_div;
43 int pll_out;
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040044 unsigned int pll_base;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050045
Tom Rini6a5dccc2022-11-16 13:10:41 -050046 pll_out = CFG_SYS_OSCIN_FREQ;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050047
48 if (id == DAVINCI_AUXCLK_CLKID)
49 goto out;
50
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040051 if ((id >> 16) == 1)
52 pll_base = (unsigned int)davinci_pllc1_regs;
53 else
54 pll_base = (unsigned int)davinci_pllc0_regs;
55
56 id &= 0xFFFF;
57
Sekhar Nori302fc2f2009-11-12 11:07:22 -050058 /*
59 * Lets keep this simple. Combining operations can result in
60 * unexpected approximations
61 */
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040062 pre_div = (readl(pll_base + PLLC_PREDIV) &
63 DAVINCI_PLLC_DIV_MASK) + 1;
64 pllm = readl(pll_base + PLLC_PLLM) + 1;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050065
66 pll_out /= pre_div;
67 pll_out *= pllm;
68
69 if (id == DAVINCI_PLLM_CLKID)
70 goto out;
71
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040072 post_div = (readl(pll_base + PLLC_POSTDIV) &
73 DAVINCI_PLLC_DIV_MASK) + 1;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050074
75 pll_out /= post_div;
76
77 if (id == DAVINCI_PLLC_CLKID)
78 goto out;
79
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040080 pll_out /= (readl(pll_base + sysdiv[id - 1]) &
81 DAVINCI_PLLC_DIV_MASK) + 1;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050082
83out:
84 return pll_out;
85}
Laurence Withersdfd07f62012-07-30 23:30:37 +000086
87int set_cpu_clk_info(void)
88{
89 gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
90 /* DDR PHY uses an x2 input clock */
91 gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
92 (clk_get(DAVINCI_DDR_CLKID) / 1000000);
93 gd->bd->bi_dsp_freq = 0;
94 return 0;
95}
Tom Riniaea2a992021-12-14 13:36:39 -050096
97unsigned long get_board_sys_clk(void)
98{
99 return clk_get(DAVINCI_ARM_CLKID);
100}