| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: ARM memory mapped architected timer |
| 8 | |
| 9 | maintainers: |
| 10 | - Marc Zyngier <marc.zyngier@arm.com> |
| 11 | - Mark Rutland <mark.rutland@arm.com> |
| 12 | |
| 13 | description: |+ |
| 14 | ARM cores may have a memory mapped architected timer, which provides up to 8 |
| 15 | frames with a physical and optional virtual timer per frame. |
| 16 | |
| 17 | The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs. |
| 18 | |
| 19 | properties: |
| 20 | compatible: |
| 21 | items: |
| 22 | - enum: |
| 23 | - arm,armv7-timer-mem |
| 24 | |
| 25 | reg: |
| 26 | maxItems: 1 |
| 27 | description: The control frame base address |
| 28 | |
| 29 | '#address-cells': |
| 30 | enum: [1, 2] |
| 31 | |
| 32 | '#size-cells': |
| 33 | const: 1 |
| 34 | |
| 35 | ranges: true |
| 36 | |
| 37 | clock-frequency: |
| 38 | description: The frequency of the main counter, in Hz. Should be present |
| 39 | only where necessary to work around broken firmware which does not configure |
| 40 | CNTFRQ on all CPUs to a uniform correct value. Use of this property is |
| 41 | strongly discouraged; fix your firmware unless absolutely impossible. |
| 42 | |
| 43 | always-on: |
| 44 | type: boolean |
| 45 | description: If present, the timer is powered through an always-on power |
| 46 | domain, therefore it never loses context. |
| 47 | |
| 48 | arm,cpu-registers-not-fw-configured: |
| 49 | type: boolean |
| 50 | description: Firmware does not initialize any of the generic timer CPU |
| 51 | registers, which contain their architecturally-defined reset values. Only |
| 52 | supported for 32-bit systems which follow the ARMv7 architected reset |
| 53 | values. |
| 54 | |
| 55 | arm,no-tick-in-suspend: |
| 56 | type: boolean |
| 57 | description: The main counter does not tick when the system is in |
| 58 | low-power system suspend on some SoCs. This behavior does not match the |
| 59 | Architecture Reference Manual's specification that the system counter "must |
| 60 | be implemented in an always-on power domain." |
| 61 | |
| 62 | patternProperties: |
| Tom Rini | 6bb92fc | 2024-05-20 09:54:58 -0600 | [diff] [blame] | 63 | '^frame@[0-9a-f]+$': |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 64 | type: object |
| 65 | additionalProperties: false |
| 66 | description: A timer node has up to 8 frame sub-nodes, each with the following properties. |
| 67 | properties: |
| 68 | frame-number: |
| 69 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 70 | minimum: 0 |
| 71 | maximum: 7 |
| 72 | |
| 73 | interrupts: |
| 74 | minItems: 1 |
| 75 | items: |
| 76 | - description: physical timer irq |
| 77 | - description: virtual timer irq |
| 78 | |
| 79 | reg: |
| 80 | minItems: 1 |
| 81 | items: |
| 82 | - description: 1st view base address |
| 83 | - description: 2nd optional view base address |
| 84 | |
| 85 | required: |
| 86 | - frame-number |
| 87 | - interrupts |
| 88 | - reg |
| 89 | |
| 90 | required: |
| 91 | - compatible |
| 92 | - reg |
| 93 | - '#address-cells' |
| 94 | - '#size-cells' |
| 95 | |
| 96 | additionalProperties: false |
| 97 | |
| 98 | examples: |
| 99 | - | |
| 100 | timer@f0000000 { |
| 101 | compatible = "arm,armv7-timer-mem"; |
| 102 | #address-cells = <1>; |
| 103 | #size-cells = <1>; |
| 104 | ranges = <0 0xf0001000 0x1000>; |
| 105 | reg = <0xf0000000 0x1000>; |
| 106 | clock-frequency = <50000000>; |
| 107 | |
| 108 | frame@0 { |
| 109 | frame-number = <0>; |
| 110 | interrupts = <0 13 0x8>, |
| 111 | <0 14 0x8>; |
| 112 | reg = <0x0000 0x1000>, |
| 113 | <0x1000 0x1000>; |
| 114 | }; |
| 115 | |
| 116 | frame@2000 { |
| 117 | frame-number = <1>; |
| 118 | interrupts = <0 15 0x8>; |
| 119 | reg = <0x2000 0x1000>; |
| 120 | }; |
| 121 | }; |
| 122 | |
| 123 | ... |