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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX System Reset Controller
8
9maintainers:
10 - Philipp Zabel <p.zabel@pengutronix.de>
11
12description: |
13 The system reset controller can be used to reset the GPU, VPU,
14 IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
15 nodes should specify the reset line on the SRC in their resets
16 property, containing a phandle to the SRC device node and a
17 RESET_INDEX specifying which module to reset, as described in
18 reset.txt
19
20 The following RESET_INDEX values are valid for i.MX5:
21 GPU_RESET 0
22 VPU_RESET 1
23 IPU1_RESET 2
24 OPEN_VG_RESET 3
25 The following additional RESET_INDEX value is valid for i.MX6:
26 IPU2_RESET 4
27
28properties:
29 compatible:
30 oneOf:
Tom Rini93743d22024-04-01 09:08:13 -040031 - const: fsl,imx51-src
Tom Rini53633a82024-02-29 12:33:36 -050032 - items:
Tom Rini93743d22024-04-01 09:08:13 -040033 - enum:
34 - fsl,imx50-src
35 - fsl,imx53-src
36 - fsl,imx6q-src
37 - fsl,imx6sx-src
38 - fsl,imx6sl-src
39 - fsl,imx6ul-src
40 - fsl,imx6sll-src
41 - const: fsl,imx51-src
Tom Rini53633a82024-02-29 12:33:36 -050042
43 reg:
44 maxItems: 1
45
46 interrupts:
47 items:
48 - description: SRC interrupt
49 - description: CPU WDOG interrupts out of SRC
50 minItems: 1
51
52 '#reset-cells':
53 const: 1
54
55required:
56 - compatible
57 - reg
58 - interrupts
59 - '#reset-cells'
60
61additionalProperties: false
62
63examples:
64 - |
65 reset-controller@73fd0000 {
66 compatible = "fsl,imx51-src";
67 reg = <0x73fd0000 0x4000>;
68 interrupts = <75>;
69 #reset-cells = <1>;
70 };