| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY |
| 8 | |
| 9 | maintainers: |
| 10 | - Krzysztof Kozlowski <krzk@kernel.org> |
| 11 | - Marek Szyprowski <m.szyprowski@samsung.com> |
| 12 | - Sylwester Nawrocki <s.nawrocki@samsung.com> |
| 13 | |
| 14 | description: | |
| 15 | For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy |
| 16 | compatible PHYs, the second cell in the PHY specifier identifies the |
| 17 | PHY id, which is interpreted as follows:: |
| 18 | 0 - UTMI+ type phy, |
| 19 | 1 - PIPE3 type phy. |
| 20 | |
| 21 | For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, |
| 22 | 'usbdrd_phy' nodes should have numbered alias in the aliases node, in the |
| 23 | form of usbdrdphyN, N = 0, 1... (depending on number of controllers). |
| 24 | |
| 25 | properties: |
| 26 | compatible: |
| 27 | enum: |
| 28 | - samsung,exynos5250-usbdrd-phy |
| 29 | - samsung,exynos5420-usbdrd-phy |
| 30 | - samsung,exynos5433-usbdrd-phy |
| 31 | - samsung,exynos7-usbdrd-phy |
| 32 | - samsung,exynos850-usbdrd-phy |
| 33 | |
| 34 | clocks: |
| 35 | minItems: 2 |
| 36 | maxItems: 5 |
| 37 | |
| 38 | clock-names: |
| 39 | minItems: 2 |
| 40 | maxItems: 5 |
| 41 | description: | |
| 42 | At least two clocks:: |
| 43 | - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used |
| 44 | for register access. |
| 45 | - PHY reference clock (usually crystal clock), used for PHY operations, |
| 46 | associated by phy name. It is used to determine bit values for clock |
| 47 | settings register. For Exynos5420 this is given as 'sclk_usbphy30' |
| 48 | in the CMU. |
| 49 | |
| 50 | "#phy-cells": |
| 51 | const: 1 |
| 52 | |
| 53 | port: |
| 54 | $ref: /schemas/graph.yaml#/properties/port |
| 55 | description: |
| 56 | Any connector to the data bus of this controller should be modelled using |
| 57 | the OF graph bindings specified. |
| 58 | |
| 59 | reg: |
| 60 | maxItems: 1 |
| 61 | |
| 62 | samsung,pmu-syscon: |
| 63 | $ref: /schemas/types.yaml#/definitions/phandle |
| 64 | description: |
| 65 | Phandle to PMU system controller interface. |
| 66 | |
| 67 | vbus-supply: |
| 68 | description: |
| 69 | VBUS power source. |
| 70 | |
| 71 | vbus-boost-supply: |
| 72 | description: |
| 73 | VBUS Boost 5V power source. |
| 74 | |
| 75 | required: |
| 76 | - compatible |
| 77 | - clocks |
| 78 | - clock-names |
| 79 | - "#phy-cells" |
| 80 | - reg |
| 81 | - samsung,pmu-syscon |
| 82 | |
| 83 | allOf: |
| 84 | - if: |
| 85 | properties: |
| 86 | compatible: |
| 87 | contains: |
| 88 | enum: |
| 89 | - samsung,exynos5433-usbdrd-phy |
| 90 | - samsung,exynos7-usbdrd-phy |
| 91 | then: |
| 92 | properties: |
| 93 | clocks: |
| 94 | minItems: 5 |
| 95 | maxItems: 5 |
| 96 | clock-names: |
| 97 | items: |
| 98 | - const: phy |
| 99 | - const: ref |
| 100 | - const: phy_utmi |
| 101 | - const: phy_pipe |
| 102 | - const: itp |
| 103 | else: |
| 104 | properties: |
| 105 | clocks: |
| 106 | minItems: 2 |
| 107 | maxItems: 2 |
| 108 | clock-names: |
| 109 | items: |
| 110 | - const: phy |
| 111 | - const: ref |
| 112 | |
| 113 | additionalProperties: false |
| 114 | |
| 115 | examples: |
| 116 | - | |
| 117 | #include <dt-bindings/clock/exynos5420.h> |
| 118 | |
| 119 | phy@12100000 { |
| 120 | compatible = "samsung,exynos5420-usbdrd-phy"; |
| 121 | reg = <0x12100000 0x100>; |
| 122 | #phy-cells = <1>; |
| 123 | clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; |
| 124 | clock-names = "phy", "ref"; |
| 125 | samsung,pmu-syscon = <&pmu_system_controller>; |
| 126 | vbus-supply = <&usb300_vbus_reg>; |
| 127 | }; |