dts/upstream/Bindings/phy/qcom,msm8998-qmp-pcie-phy.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QMP PHY controller (PCIe, MSM8998)

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  The QMP PHY controller supports physical layer functionality for a number of
  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

properties:
  compatible:
    const: qcom,msm8998-qmp-pcie-phy

  reg:
    items:
      - description: serdes

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: aux
      - const: cfg_ahb
      - const: ref
      - const: pipe

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: phy
      - const: common

  vdda-phy-supply: true

  vdda-pll-supply: true

  "#clock-cells":
    const: 0

  clock-output-names:
    maxItems: 1

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - vdda-phy-supply
  - vdda-pll-supply
  - "#clock-cells"
  - clock-output-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8998.h>

    phy@1c18000 {
        compatible = "qcom,msm8998-qmp-pcie-phy";
        reg = <0x01c06000 0x1000>;

        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                 <&gcc GCC_PCIE_CLKREF_CLK>,
                 <&gcc GCC_PCIE_0_PIPE_CLK>;
        clock-names = "aux",
                      "cfg_ahb",
                      "ref",
                      "pipe";

        clock-output-names = "pcie_0_pipe_clk_src";
        #clock-cells = <0>;

        #phy-cells = <0>;

        resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
        reset-names = "phy", "common";

        vdda-phy-supply = <&vreg_l1a_0p875>;
        vdda-pll-supply = <&vreg_l2a_1p2>;
    };