| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Socionext UniPhier PCIe endpoint controller |
| 8 | |
| 9 | description: | |
| 10 | UniPhier PCIe endpoint controller is based on the Synopsys DesignWare |
| 11 | PCI core. It shares common features with the PCIe DesignWare core and |
| 12 | inherits common properties defined in |
| 13 | Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml. |
| 14 | |
| 15 | maintainers: |
| 16 | - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | enum: |
| 21 | - socionext,uniphier-pro5-pcie-ep |
| 22 | - socionext,uniphier-nx1-pcie-ep |
| 23 | |
| 24 | reg: |
| 25 | minItems: 4 |
| 26 | maxItems: 5 |
| 27 | |
| 28 | reg-names: |
| 29 | minItems: 4 |
| 30 | items: |
| 31 | - const: dbi |
| 32 | - const: dbi2 |
| 33 | - const: link |
| 34 | - const: addr_space |
| 35 | - const: atu |
| 36 | |
| 37 | clocks: |
| 38 | minItems: 1 |
| 39 | maxItems: 2 |
| 40 | |
| 41 | clock-names: true |
| 42 | |
| 43 | resets: |
| 44 | minItems: 1 |
| 45 | maxItems: 2 |
| 46 | |
| 47 | reset-names: true |
| 48 | |
| 49 | num-ib-windows: |
| 50 | const: 16 |
| 51 | |
| 52 | num-ob-windows: |
| 53 | const: 16 |
| 54 | |
| 55 | num-lanes: true |
| 56 | |
| 57 | phys: |
| 58 | maxItems: 1 |
| 59 | |
| 60 | phy-names: |
| 61 | const: pcie-phy |
| 62 | |
| 63 | allOf: |
| 64 | - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# |
| 65 | - if: |
| 66 | properties: |
| 67 | compatible: |
| 68 | contains: |
| 69 | const: socionext,uniphier-pro5-pcie-ep |
| 70 | then: |
| 71 | properties: |
| 72 | reg: |
| 73 | maxItems: 4 |
| 74 | reg-names: |
| 75 | maxItems: 4 |
| 76 | clocks: |
| 77 | minItems: 2 |
| 78 | clock-names: |
| 79 | items: |
| 80 | - const: gio |
| 81 | - const: link |
| 82 | resets: |
| 83 | minItems: 2 |
| 84 | reset-names: |
| 85 | items: |
| 86 | - const: gio |
| 87 | - const: link |
| 88 | else: |
| 89 | properties: |
| 90 | reg: |
| 91 | minItems: 5 |
| 92 | reg-names: |
| 93 | minItems: 5 |
| 94 | clocks: |
| 95 | maxItems: 1 |
| 96 | clock-names: |
| 97 | const: link |
| 98 | resets: |
| 99 | maxItems: 1 |
| 100 | reset-names: |
| 101 | const: link |
| 102 | |
| 103 | required: |
| 104 | - compatible |
| 105 | - reg |
| 106 | - reg-names |
| 107 | - clocks |
| 108 | - clock-names |
| 109 | - resets |
| 110 | - reset-names |
| 111 | |
| 112 | unevaluatedProperties: false |
| 113 | |
| 114 | examples: |
| 115 | - | |
| 116 | pcie_ep: pcie-ep@66000000 { |
| 117 | compatible = "socionext,uniphier-pro5-pcie-ep"; |
| 118 | reg-names = "dbi", "dbi2", "link", "addr_space"; |
| 119 | reg = <0x66000000 0x1000>, <0x66001000 0x1000>, |
| 120 | <0x66010000 0x10000>, <0x67000000 0x400000>; |
| 121 | clock-names = "gio", "link"; |
| 122 | clocks = <&sys_clk 12>, <&sys_clk 24>; |
| 123 | reset-names = "gio", "link"; |
| 124 | resets = <&sys_rst 12>, <&sys_rst 24>; |
| 125 | num-ib-windows = <16>; |
| 126 | num-ob-windows = <16>; |
| 127 | num-lanes = <4>; |
| 128 | phy-names = "pcie-phy"; |
| 129 | phys = <&pcie_phy>; |
| 130 | }; |