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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Ethernet Controller Common Properties
8
9maintainers:
10 - David S. Miller <davem@davemloft.net>
11
12properties:
13 $nodename:
14 pattern: "^ethernet(@.*)?$"
15
16 label:
Tom Rini53633a82024-02-29 12:33:36 -050017 description: Human readable label on a port of a box.
18
19 local-mac-address:
20 description:
21 Specifies the MAC address that was assigned to the network device.
22 $ref: /schemas/types.yaml#/definitions/uint8-array
23 minItems: 6
24 maxItems: 6
25
26 mac-address:
27 description:
28 Specifies the MAC address that was last used by the boot
29 program; should be used in cases where the MAC address assigned
30 to the device by the boot program is different from the
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
33 minItems: 6
34 maxItems: 6
35
36 max-frame-size:
37 $ref: /schemas/types.yaml#/definitions/uint32
38 description:
39 Maximum transfer unit (IEEE defined MTU), rather than the
40 maximum frame size (there\'s contradiction in the Devicetree
41 Specification).
42
43 max-speed:
44 $ref: /schemas/types.yaml#/definitions/uint32
45 description:
46 Specifies maximum speed in Mbit/s supported by the device.
47
48 nvmem-cells:
49 maxItems: 1
50 description:
51 Reference to an nvmem node for the MAC address
52
53 nvmem-cell-names:
54 const: mac-address
55
56 phy-connection-type:
57 description:
58 Specifies interface type between the Ethernet device and a physical
59 layer (PHY) device.
60 enum:
61 # There is not a standard bus between the MAC and the PHY,
62 # something proprietary is being used to embed the PHY in the
63 # MAC.
64 - internal
65 - mii
66 - gmii
67 - sgmii
68 - psgmii
69 - qsgmii
70 - qusgmii
71 - tbi
72 - rev-mii
73 - rmii
74 - rev-rmii
75 - moca
76
77 # RX and TX delays are added by the MAC when required
78 - rgmii
79
80 # RGMII with internal RX and TX delays provided by the PHY,
81 # the MAC should not add the RX or TX delays in this case
82 - rgmii-id
83
84 # RGMII with internal RX delay provided by the PHY, the MAC
85 # should not add an RX delay in this case
86 - rgmii-rxid
87
88 # RGMII with internal TX delay provided by the PHY, the MAC
89 # should not add an TX delay in this case
90 - rgmii-txid
91 - rtbi
92 - smii
93 - xgmii
94 - trgmii
95 - 1000base-x
96 - 2500base-x
97 - 5gbase-r
98 - rxaui
99 - xaui
100
101 # 10GBASE-KR, XFI, SFI
102 - 10gbase-kr
103 - usxgmii
104 - 10gbase-r
105 - 25gbase-r
106
107 phy-mode:
108 $ref: "#/properties/phy-connection-type"
109
110 pcs-handle:
111 $ref: /schemas/types.yaml#/definitions/phandle-array
112 items:
113 maxItems: 1
114 description:
115 Specifies a reference to a node representing a PCS PHY device on a MDIO
116 bus to link with an external PHY (phy-handle) if exists.
117
118 pcs-handle-names:
119 description:
120 The name of each PCS in pcs-handle.
121
122 phy-handle:
123 $ref: /schemas/types.yaml#/definitions/phandle
124 description:
125 Specifies a reference to a node representing a PHY device.
126
127 phy:
128 $ref: "#/properties/phy-handle"
129 deprecated: true
130
131 phy-device:
132 $ref: "#/properties/phy-handle"
133 deprecated: true
134
135 rx-fifo-depth:
136 $ref: /schemas/types.yaml#/definitions/uint32
137 description:
138 The size of the controller\'s receive fifo in bytes. This is used
139 for components that can have configurable receive fifo sizes,
140 and is useful for determining certain configuration settings
141 such as flow control thresholds.
142
143 sfp:
144 $ref: /schemas/types.yaml#/definitions/phandle
145 description:
146 Specifies a reference to a node representing a SFP cage.
147
148 tx-fifo-depth:
149 $ref: /schemas/types.yaml#/definitions/uint32
150 description:
151 The size of the controller\'s transmit fifo in bytes. This
152 is used for components that can have configurable fifo sizes.
153
154 managed:
155 description:
156 Specifies the PHY management type. If auto is set and fixed-link
157 is not specified, it uses MDIO for management.
158 $ref: /schemas/types.yaml#/definitions/string
159 default: auto
160 enum:
161 - auto
162 - in-band-status
163
164 fixed-link:
165 oneOf:
166 - $ref: /schemas/types.yaml#/definitions/uint32-array
167 deprecated: true
168 items:
169 - minimum: 0
170 maximum: 31
171 description:
172 Emulated PHY ID, choose any but unique to the all
173 specified fixed-links
174
175 - enum: [0, 1]
176 description:
177 Duplex configuration. 0 for half duplex or 1 for
178 full duplex
179
180 - enum: [10, 100, 1000, 2500, 10000]
181 description:
182 Link speed in Mbits/sec.
183
184 - enum: [0, 1]
185 description:
186 Pause configuration. 0 for no pause, 1 for pause
187
188 - enum: [0, 1]
189 description:
190 Asymmetric pause configuration. 0 for no asymmetric
191 pause, 1 for asymmetric pause
192 - type: object
193 additionalProperties: false
194 properties:
195 speed:
196 description:
197 Link speed.
198 $ref: /schemas/types.yaml#/definitions/uint32
199 enum: [10, 100, 1000, 2500, 10000]
200
201 full-duplex:
202 $ref: /schemas/types.yaml#/definitions/flag
203 description:
204 Indicates that full-duplex is used. When absent, half
205 duplex is assumed.
206
207 pause:
208 $ref: /schemas/types.yaml#/definitions/flag
209 description:
210 Indicates that pause should be enabled.
211
212 asym-pause:
213 $ref: /schemas/types.yaml#/definitions/flag
214 description:
215 Indicates that asym_pause should be enabled.
216
217 link-gpios:
218 maxItems: 1
219 description:
220 GPIO to determine if the link is up
221
222 required:
223 - speed
224
225 leds:
226 description:
227 Describes the LEDs associated by Ethernet Controller.
228 These LEDs are not integrated in the PHY and PHY doesn't have any
229 control on them. Ethernet Controller regs are used to control
230 these defined LEDs.
231
232 type: object
233
234 properties:
235 '#address-cells':
236 const: 1
237
238 '#size-cells':
239 const: 0
240
241 patternProperties:
242 '^led@[a-f0-9]+$':
243 $ref: /schemas/leds/common.yaml#
244
245 properties:
246 reg:
247 maxItems: 1
248 description:
249 This define the LED index in the PHY or the MAC. It's really
250 driver dependent and required for ports that define multiple
251 LED for the same port.
252
253 required:
254 - reg
255
256 unevaluatedProperties: false
257
258 additionalProperties: false
259
260dependencies:
261 pcs-handle-names: [pcs-handle]
262
263allOf:
264 - if:
265 properties:
266 phy-mode:
267 contains:
268 enum:
269 - rgmii
270 - rgmii-rxid
271 - rgmii-txid
272 - rgmii-id
273 then:
274 properties:
275 rx-internal-delay-ps:
276 description:
277 RGMII Receive Clock Delay defined in pico seconds. This is used for
278 controllers that have configurable RX internal delays. If this
279 property is present then the MAC applies the RX delay.
280 tx-internal-delay-ps:
281 description:
282 RGMII Transmit Clock Delay defined in pico seconds. This is used for
283 controllers that have configurable TX internal delays. If this
284 property is present then the MAC applies the TX delay.
285
286additionalProperties: true
287
288...