| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Technologies legacy IOMMU implementations |
| 8 | |
| 9 | maintainers: |
| 10 | - Konrad Dybcio <konrad.dybcio@linaro.org> |
| 11 | |
| 12 | description: | |
| 13 | Qualcomm "B" family devices which are not compatible with arm-smmu have |
| 14 | a similar looking IOMMU, but without access to the global register space |
| 15 | and optionally requiring additional configuration to route context IRQs |
| 16 | to non-secure vs secure interrupt line. |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | oneOf: |
| 21 | - items: |
| 22 | - enum: |
| 23 | - qcom,msm8916-iommu |
| 24 | - qcom,msm8953-iommu |
| 25 | - const: qcom,msm-iommu-v1 |
| 26 | - items: |
| 27 | - enum: |
| 28 | - qcom,msm8976-iommu |
| 29 | - const: qcom,msm-iommu-v2 |
| 30 | |
| 31 | clocks: |
| 32 | items: |
| 33 | - description: Clock required for IOMMU register group access |
| 34 | - description: Clock required for underlying bus access |
| 35 | |
| 36 | clock-names: |
| 37 | items: |
| 38 | - const: iface |
| 39 | - const: bus |
| 40 | |
| 41 | power-domains: |
| 42 | maxItems: 1 |
| 43 | |
| 44 | reg: |
| 45 | maxItems: 1 |
| 46 | |
| 47 | ranges: true |
| 48 | |
| 49 | qcom,iommu-secure-id: |
| 50 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 51 | description: |
| 52 | The SCM secure ID of the IOMMU instance. |
| 53 | |
| 54 | '#address-cells': |
| 55 | const: 1 |
| 56 | |
| 57 | '#size-cells': |
| 58 | const: 1 |
| 59 | |
| 60 | '#iommu-cells': |
| 61 | const: 1 |
| 62 | |
| 63 | patternProperties: |
| 64 | "^iommu-ctx@[0-9a-f]+$": |
| 65 | type: object |
| 66 | additionalProperties: false |
| 67 | properties: |
| 68 | compatible: |
| 69 | enum: |
| 70 | - qcom,msm-iommu-v1-ns |
| 71 | - qcom,msm-iommu-v1-sec |
| 72 | - qcom,msm-iommu-v2-ns |
| 73 | - qcom,msm-iommu-v2-sec |
| 74 | |
| 75 | interrupts: |
| 76 | maxItems: 1 |
| 77 | |
| 78 | reg: |
| 79 | maxItems: 1 |
| 80 | |
| 81 | qcom,ctx-asid: |
| 82 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 83 | description: |
| 84 | The ASID number associated to the context bank. |
| 85 | |
| 86 | required: |
| 87 | - compatible |
| 88 | - interrupts |
| 89 | - reg |
| 90 | |
| 91 | required: |
| 92 | - compatible |
| 93 | - clocks |
| 94 | - clock-names |
| 95 | - ranges |
| 96 | - '#address-cells' |
| 97 | - '#size-cells' |
| 98 | - '#iommu-cells' |
| 99 | |
| 100 | additionalProperties: false |
| 101 | |
| 102 | examples: |
| 103 | - | |
| 104 | #include <dt-bindings/clock/qcom,gcc-msm8916.h> |
| 105 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 106 | |
| 107 | apps_iommu: iommu@1e20000 { |
| 108 | compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; |
| 109 | reg = <0x01ef0000 0x3000>; |
| 110 | clocks = <&gcc GCC_SMMU_CFG_CLK>, |
| 111 | <&gcc GCC_APSS_TCU_CLK>; |
| 112 | clock-names = "iface", "bus"; |
| 113 | qcom,iommu-secure-id = <17>; |
| 114 | #address-cells = <1>; |
| 115 | #size-cells = <1>; |
| 116 | #iommu-cells = <1>; |
| 117 | ranges = <0 0x01e20000 0x40000>; |
| 118 | |
| 119 | /* mdp_0: */ |
| 120 | iommu-ctx@4000 { |
| 121 | compatible = "qcom,msm-iommu-v1-ns"; |
| 122 | reg = <0x4000 0x1000>; |
| 123 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 124 | }; |
| 125 | }; |