Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 |
| 8 | |
| 9 | maintainers: |
| 10 | - Taniya Das <quic_tdas@quicinc.com> |
| 11 | - Imran Shaik <quic_imrashai@quicinc.com> |
| 12 | |
| 13 | description: | |
| 14 | Qualcomm global clock control module which supports the clocks, resets and |
| 15 | power domains on QDU1000 and QRU1000 |
| 16 | |
| 17 | See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h |
| 18 | |
| 19 | properties: |
| 20 | compatible: |
| 21 | const: qcom,qdu1000-gcc |
| 22 | |
| 23 | clocks: |
| 24 | items: |
| 25 | - description: Board XO source |
| 26 | - description: Sleep clock source |
| 27 | - description: PCIE 0 Pipe clock source |
| 28 | - description: PCIE 0 Phy Auxiliary clock source |
| 29 | - description: USB3 Phy wrapper pipe clock source |
| 30 | |
| 31 | required: |
| 32 | - compatible |
| 33 | - clocks |
| 34 | |
| 35 | allOf: |
| 36 | - $ref: qcom,gcc.yaml# |
| 37 | |
| 38 | unevaluatedProperties: false |
| 39 | |
| 40 | examples: |
| 41 | - | |
| 42 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 43 | clock-controller@100000 { |
| 44 | compatible = "qcom,qdu1000-gcc"; |
| 45 | reg = <0x00100000 0x001f4200>; |
| 46 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, |
| 47 | <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>, |
| 48 | <&usb3_phy_wrapper_pipe_clk>; |
| 49 | #clock-cells = <1>; |
| 50 | #reset-cells = <1>; |
| 51 | #power-domain-cells = <1>; |
| 52 | }; |