dts/upstream/Bindings/clock/mediatek,mt8365-sys-clock.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek System Clock Controller for MT8365

maintainers:
  - Markus Schneider-Pargmann <msp@baylibre.com>

description:
  The apmixedsys module provides most of PLLs which generated from SoC 26m.
  The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
  The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8365-topckgen
          - mediatek,mt8365-infracfg
          - mediatek,mt8365-apmixedsys
          - mediatek,mt8365-pericfg
          - mediatek,mt8365-mcucfg
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    topckgen: clock-controller@10000000 {
        compatible = "mediatek,mt8365-topckgen", "syscon";
        reg = <0x10000000 0x1000>;
        #clock-cells = <1>;
    };