| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | PLL divider based Dove clocks |
| 2 | |
| 3 | Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide |
| 4 | high speed clocks for a number of peripherals. These dividers are part of |
| 5 | the PMU, and thus this node should be a child of the PMU node. |
| 6 | |
| 7 | The following clocks are provided: |
| 8 | |
| 9 | ID Clock |
| 10 | ------------- |
| 11 | 0 AXI bus clock |
| 12 | 1 GPU clock |
| 13 | 2 VMeta clock |
| 14 | 3 LCD clock |
| 15 | |
| 16 | Required properties: |
| 17 | - compatible : shall be "marvell,dove-divider-clock" |
| 18 | - reg : shall be the register address of the Core PLL and Clock Divider |
| 19 | Control 0 register. This will cover that register, as well as the |
| 20 | Core PLL and Clock Divider Control 1 register. Thus, it will have |
| 21 | a size of 8. |
| 22 | - #clock-cells : from common clock binding; shall be set to 1 |
| 23 | |
| 24 | divider_clk: core-clock@64 { |
| 25 | compatible = "marvell,dove-divider-clock"; |
| 26 | reg = <0x0064 0x8>; |
| 27 | #clock-cells = <1>; |
| 28 | }; |