Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 6 | #include <clk.h> |
| 7 | #include <display.h> |
| 8 | #include <dm.h> |
| 9 | #include <dw_hdmi.h> |
| 10 | #include <edid.h> |
| 11 | #include <regmap.h> |
| 12 | #include <syscon.h> |
| 13 | #include <asm/gpio.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 14 | #include <asm/arch-rockchip/clock.h> |
| 15 | #include <asm/arch-rockchip/hardware.h> |
| 16 | #include <asm/arch-rockchip/grf_rk3399.h> |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 17 | #include <power/regulator.h> |
| 18 | #include "rk_hdmi.h" |
| 19 | |
| 20 | static int rk3399_hdmi_enable(struct udevice *dev, int panel_bpp, |
| 21 | const struct display_timing *edid) |
| 22 | { |
| 23 | struct rk_hdmi_priv *priv = dev_get_priv(dev); |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 24 | struct display_plat *uc_plat = dev_get_uclass_plat(dev); |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 25 | int vop_id = uc_plat->source_id; |
| 26 | struct rk3399_grf_regs *grf = priv->grf; |
| 27 | |
| 28 | /* select the hdmi encoder input data from our source_id */ |
| 29 | rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK, |
| 30 | (vop_id == 1) ? GRF_RK3399_HDMI_VOP_SEL_L : 0); |
| 31 | |
| 32 | return dw_hdmi_enable(&priv->hdmi, edid); |
| 33 | } |
| 34 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 35 | static int rk3399_hdmi_of_to_plat(struct udevice *dev) |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 36 | { |
| 37 | struct rk_hdmi_priv *priv = dev_get_priv(dev); |
| 38 | struct dw_hdmi *hdmi = &priv->hdmi; |
| 39 | |
| 40 | hdmi->i2c_clk_high = 0x7a; |
| 41 | hdmi->i2c_clk_low = 0x8d; |
| 42 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 43 | return rk_hdmi_of_to_plat(dev); |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 44 | } |
| 45 | |
| 46 | static const char * const rk3399_regulator_names[] = { |
| 47 | "vcc1v8_hdmi", |
| 48 | "vcc0v9_hdmi" |
| 49 | }; |
| 50 | |
| 51 | static int rk3399_hdmi_probe(struct udevice *dev) |
| 52 | { |
| 53 | /* Enable regulators required for HDMI */ |
| 54 | rk_hdmi_probe_regulators(dev, rk3399_regulator_names, |
| 55 | ARRAY_SIZE(rk3399_regulator_names)); |
| 56 | |
| 57 | return rk_hdmi_probe(dev); |
| 58 | } |
| 59 | |
| 60 | static const struct dm_display_ops rk3399_hdmi_ops = { |
| 61 | .read_edid = rk_hdmi_read_edid, |
| 62 | .enable = rk3399_hdmi_enable, |
| 63 | }; |
| 64 | |
| 65 | static const struct udevice_id rk3399_hdmi_ids[] = { |
| 66 | { .compatible = "rockchip,rk3399-dw-hdmi" }, |
| 67 | { } |
| 68 | }; |
| 69 | |
| 70 | U_BOOT_DRIVER(rk3399_hdmi_rockchip) = { |
| 71 | .name = "rk3399_hdmi_rockchip", |
| 72 | .id = UCLASS_DISPLAY, |
| 73 | .of_match = rk3399_hdmi_ids, |
| 74 | .ops = &rk3399_hdmi_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 75 | .of_to_plat = rk3399_hdmi_of_to_plat, |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 76 | .probe = rk3399_hdmi_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 77 | .priv_auto = sizeof(struct rk_hdmi_priv), |
Philipp Tomsich | df48c79 | 2017-05-31 17:59:34 +0200 | [diff] [blame] | 78 | }; |