developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * MediaTek High-speed UART driver |
| 4 | * |
| 5 | * Copyright (C) 2018 MediaTek Inc. |
| 6 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #include <clk.h> |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 10 | #include <config.h> |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 11 | #include <div64.h> |
| 12 | #include <dm.h> |
Christian Marangi | 83add96 | 2024-06-24 23:03:33 +0200 | [diff] [blame] | 13 | #include <dm/device.h> |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 14 | #include <dm/device_compat.h> |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 15 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 16 | #include <log.h> |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 17 | #include <serial.h> |
| 18 | #include <watchdog.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 19 | #include <asm/global_data.h> |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 20 | #include <asm/io.h> |
| 21 | #include <asm/types.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 22 | #include <linux/err.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame] | 23 | #include <linux/printk.h> |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 24 | |
| 25 | struct mtk_serial_regs { |
| 26 | u32 rbr; |
| 27 | u32 ier; |
| 28 | u32 fcr; |
| 29 | u32 lcr; |
| 30 | u32 mcr; |
| 31 | u32 lsr; |
| 32 | u32 msr; |
| 33 | u32 spr; |
| 34 | u32 mdr1; |
| 35 | u32 highspeed; |
| 36 | u32 sample_count; |
| 37 | u32 sample_point; |
| 38 | u32 fracdiv_l; |
| 39 | u32 fracdiv_m; |
| 40 | u32 escape_en; |
| 41 | u32 guard; |
| 42 | u32 rx_sel; |
| 43 | }; |
| 44 | |
| 45 | #define thr rbr |
| 46 | #define iir fcr |
| 47 | #define dll rbr |
| 48 | #define dlm ier |
| 49 | |
| 50 | #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ |
| 51 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
| 52 | |
| 53 | #define UART_LSR_DR 0x01 /* Data ready */ |
| 54 | #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ |
developer | 67d2b61 | 2019-09-25 17:45:17 +0800 | [diff] [blame] | 55 | #define UART_LSR_TEMT 0x40 /* Xmitter empty */ |
| 56 | |
| 57 | #define UART_MCR_DTR 0x01 /* DTR */ |
| 58 | #define UART_MCR_RTS 0x02 /* RTS */ |
| 59 | |
| 60 | #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ |
| 61 | #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ |
| 62 | #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ |
| 63 | |
| 64 | #define UART_MCRVAL (UART_MCR_DTR | \ |
| 65 | UART_MCR_RTS) |
| 66 | |
| 67 | /* Clear & enable FIFOs */ |
| 68 | #define UART_FCRVAL (UART_FCR_FIFO_EN | \ |
| 69 | UART_FCR_RXSR | \ |
| 70 | UART_FCR_TXSR) |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 71 | |
| 72 | /* the data is correct if the real baud is within 3%. */ |
| 73 | #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100) |
| 74 | #define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100) |
| 75 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 76 | /* struct mtk_serial_priv - Structure holding all information used by the |
| 77 | * driver |
| 78 | * @regs: Register base of the serial port |
| 79 | * @clk: The baud clock device |
Christian Marangi | fb43868 | 2024-06-24 23:03:32 +0200 | [diff] [blame] | 80 | * @clk_bus: The bus clock device |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 81 | * @fixed_clk_rate: Fallback fixed baud clock rate if baud clock |
| 82 | * device is not specified |
| 83 | * @force_highspeed: Force using high-speed mode |
Christian Marangi | 83add96 | 2024-06-24 23:03:33 +0200 | [diff] [blame] | 84 | * @upstream_highspeed_logic: Apply upstream high-speed logic |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 85 | */ |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 86 | struct mtk_serial_priv { |
| 87 | struct mtk_serial_regs __iomem *regs; |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 88 | struct clk clk; |
Christian Marangi | fb43868 | 2024-06-24 23:03:32 +0200 | [diff] [blame] | 89 | struct clk clk_bus; |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 90 | u32 fixed_clk_rate; |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 91 | bool force_highspeed; |
Christian Marangi | 83add96 | 2024-06-24 23:03:33 +0200 | [diff] [blame] | 92 | bool upstream_highspeed_logic; |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 93 | }; |
| 94 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 95 | static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud, |
| 96 | uint clk_rate) |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 97 | { |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 98 | u32 quot, realbaud, samplecount = 1; |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 99 | |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 100 | /* Special case for low baud clock */ |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 101 | if (baud <= 115200 && clk_rate == 12000000) { |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 102 | writel(3, &priv->regs->highspeed); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 103 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 104 | quot = DIV_ROUND_CLOSEST(clk_rate, 256 * baud); |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 105 | if (quot == 0) |
| 106 | quot = 1; |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 107 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 108 | samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 109 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 110 | realbaud = clk_rate / samplecount / quot; |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 111 | if (realbaud > BAUD_ALLOW_MAX(baud) || |
| 112 | realbaud < BAUD_ALLOW_MIX(baud)) { |
| 113 | pr_info("baud %d can't be handled\n", baud); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 114 | } |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 115 | |
| 116 | goto set_baud; |
| 117 | } |
| 118 | |
Christian Marangi | 83add96 | 2024-06-24 23:03:33 +0200 | [diff] [blame] | 119 | /* |
| 120 | * Upstream linux use highspeed for anything >= 115200 and lowspeed |
| 121 | * for < 115200. Simulate this if we are using the upstream compatible. |
| 122 | */ |
| 123 | if (priv->force_highspeed || |
| 124 | (priv->upstream_highspeed_logic && baud >= 115200)) |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 125 | goto use_hs3; |
| 126 | |
| 127 | if (baud <= 115200) { |
| 128 | writel(0, &priv->regs->highspeed); |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 129 | quot = DIV_ROUND_CLOSEST(clk_rate, 16 * baud); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 130 | } else if (baud <= 576000) { |
| 131 | writel(2, &priv->regs->highspeed); |
| 132 | |
| 133 | /* Set to next lower baudrate supported */ |
| 134 | if ((baud == 500000) || (baud == 576000)) |
| 135 | baud = 460800; |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 136 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 137 | quot = DIV_ROUND_UP(clk_rate, 4 * baud); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 138 | } else { |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 139 | use_hs3: |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 140 | writel(3, &priv->regs->highspeed); |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 141 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 142 | quot = DIV_ROUND_UP(clk_rate, 256 * baud); |
| 143 | samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 144 | } |
| 145 | |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 146 | set_baud: |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 147 | /* set divisor */ |
| 148 | writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr); |
| 149 | writel(quot & 0xff, &priv->regs->dll); |
| 150 | writel((quot >> 8) & 0xff, &priv->regs->dlm); |
| 151 | writel(UART_LCR_WLS_8, &priv->regs->lcr); |
| 152 | |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 153 | /* set highspeed mode sample count & point */ |
| 154 | writel(samplecount - 1, &priv->regs->sample_count); |
| 155 | writel((samplecount - 2) >> 1, &priv->regs->sample_point); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 156 | } |
| 157 | |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 158 | static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch) |
| 159 | { |
| 160 | if (!(readl(&priv->regs->lsr) & UART_LSR_THRE)) |
| 161 | return -EAGAIN; |
| 162 | |
| 163 | writel(ch, &priv->regs->thr); |
| 164 | |
| 165 | if (ch == '\n') |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 166 | schedule(); |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 167 | |
| 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | static int _mtk_serial_getc(struct mtk_serial_priv *priv) |
| 172 | { |
| 173 | if (!(readl(&priv->regs->lsr) & UART_LSR_DR)) |
| 174 | return -EAGAIN; |
| 175 | |
| 176 | return readl(&priv->regs->rbr); |
| 177 | } |
| 178 | |
| 179 | static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input) |
| 180 | { |
| 181 | if (input) |
| 182 | return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0; |
| 183 | else |
| 184 | return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1; |
| 185 | } |
| 186 | |
Tom Rini | 952cc38 | 2022-12-04 10:14:13 -0500 | [diff] [blame] | 187 | #if CONFIG_IS_ENABLED(DM_SERIAL) |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 188 | static int mtk_serial_setbrg(struct udevice *dev, int baudrate) |
| 189 | { |
| 190 | struct mtk_serial_priv *priv = dev_get_priv(dev); |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 191 | u32 clk_rate; |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 192 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 193 | clk_rate = clk_get_rate(&priv->clk); |
| 194 | if (IS_ERR_VALUE(clk_rate) || clk_rate == 0) |
| 195 | clk_rate = priv->fixed_clk_rate; |
| 196 | |
| 197 | _mtk_serial_setbrg(priv, baudrate, clk_rate); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static int mtk_serial_putc(struct udevice *dev, const char ch) |
| 203 | { |
| 204 | struct mtk_serial_priv *priv = dev_get_priv(dev); |
| 205 | |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 206 | return _mtk_serial_putc(priv, ch); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | static int mtk_serial_getc(struct udevice *dev) |
| 210 | { |
| 211 | struct mtk_serial_priv *priv = dev_get_priv(dev); |
| 212 | |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 213 | return _mtk_serial_getc(priv); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | static int mtk_serial_pending(struct udevice *dev, bool input) |
| 217 | { |
| 218 | struct mtk_serial_priv *priv = dev_get_priv(dev); |
| 219 | |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 220 | return _mtk_serial_pending(priv, input); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | static int mtk_serial_probe(struct udevice *dev) |
| 224 | { |
| 225 | struct mtk_serial_priv *priv = dev_get_priv(dev); |
| 226 | |
| 227 | /* Disable interrupt */ |
| 228 | writel(0, &priv->regs->ier); |
| 229 | |
developer | 67d2b61 | 2019-09-25 17:45:17 +0800 | [diff] [blame] | 230 | writel(UART_MCRVAL, &priv->regs->mcr); |
| 231 | writel(UART_FCRVAL, &priv->regs->fcr); |
| 232 | |
Christian Marangi | fb43868 | 2024-06-24 23:03:32 +0200 | [diff] [blame] | 233 | clk_enable(&priv->clk); |
| 234 | if (priv->clk_bus.dev) |
| 235 | clk_enable(&priv->clk_bus); |
| 236 | |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 237 | return 0; |
| 238 | } |
| 239 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 240 | static int mtk_serial_of_to_plat(struct udevice *dev) |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 241 | { |
| 242 | struct mtk_serial_priv *priv = dev_get_priv(dev); |
| 243 | fdt_addr_t addr; |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 244 | int err; |
| 245 | |
| 246 | addr = dev_read_addr(dev); |
| 247 | if (addr == FDT_ADDR_T_NONE) |
| 248 | return -EINVAL; |
| 249 | |
| 250 | priv->regs = map_physmem(addr, 0, MAP_NOCACHE); |
| 251 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 252 | err = clk_get_by_index(dev, 0, &priv->clk); |
| 253 | if (err) { |
| 254 | err = dev_read_u32(dev, "clock-frequency", &priv->fixed_clk_rate); |
| 255 | if (err) { |
| 256 | dev_err(dev, "baud clock not defined\n"); |
| 257 | return -EINVAL; |
| 258 | } |
| 259 | } else { |
| 260 | err = clk_get_rate(&priv->clk); |
| 261 | if (IS_ERR_VALUE(err)) { |
| 262 | dev_err(dev, "invalid baud clock\n"); |
| 263 | return -EINVAL; |
| 264 | } |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 265 | } |
| 266 | |
Christian Marangi | fb43868 | 2024-06-24 23:03:32 +0200 | [diff] [blame] | 267 | clk_get_by_name(dev, "bus", &priv->clk_bus); |
| 268 | |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 269 | priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed"); |
Christian Marangi | 83add96 | 2024-06-24 23:03:33 +0200 | [diff] [blame] | 270 | priv->upstream_highspeed_logic = |
| 271 | device_is_compatible(dev, "mediatek,mt6577-uart"); |
developer | dc45773 | 2021-03-05 10:35:39 +0800 | [diff] [blame] | 272 | |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 273 | return 0; |
| 274 | } |
| 275 | |
| 276 | static const struct dm_serial_ops mtk_serial_ops = { |
| 277 | .putc = mtk_serial_putc, |
| 278 | .pending = mtk_serial_pending, |
| 279 | .getc = mtk_serial_getc, |
| 280 | .setbrg = mtk_serial_setbrg, |
| 281 | }; |
| 282 | |
| 283 | static const struct udevice_id mtk_serial_ids[] = { |
| 284 | { .compatible = "mediatek,hsuart" }, |
| 285 | { .compatible = "mediatek,mt6577-uart" }, |
| 286 | { } |
| 287 | }; |
| 288 | |
| 289 | U_BOOT_DRIVER(serial_mtk) = { |
| 290 | .name = "serial_mtk", |
| 291 | .id = UCLASS_SERIAL, |
| 292 | .of_match = mtk_serial_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 293 | .of_to_plat = mtk_serial_of_to_plat, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 294 | .priv_auto = sizeof(struct mtk_serial_priv), |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 295 | .probe = mtk_serial_probe, |
| 296 | .ops = &mtk_serial_ops, |
| 297 | .flags = DM_FLAG_PRE_RELOC, |
| 298 | }; |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 299 | #else |
| 300 | |
| 301 | DECLARE_GLOBAL_DATA_PTR; |
| 302 | |
| 303 | #define DECLARE_HSUART_PRIV(port) \ |
| 304 | static struct mtk_serial_priv mtk_hsuart##port = { \ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 305 | .regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \ |
| 306 | .fixed_clk_rate = CFG_SYS_NS16550_CLK \ |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 307 | }; |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 308 | |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 309 | #define DECLARE_HSUART_FUNCTIONS(port) \ |
| 310 | static int mtk_serial##port##_init(void) \ |
| 311 | { \ |
| 312 | writel(0, &mtk_hsuart##port.regs->ier); \ |
| 313 | writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \ |
| 314 | writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \ |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 315 | _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \ |
| 316 | mtk_hsuart##port.fixed_clk_rate); \ |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 317 | return 0 ; \ |
| 318 | } \ |
| 319 | static void mtk_serial##port##_setbrg(void) \ |
| 320 | { \ |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 321 | _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \ |
| 322 | mtk_hsuart##port.fixed_clk_rate); \ |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 323 | } \ |
| 324 | static int mtk_serial##port##_getc(void) \ |
| 325 | { \ |
| 326 | int err; \ |
| 327 | do { \ |
| 328 | err = _mtk_serial_getc(&mtk_hsuart##port); \ |
| 329 | if (err == -EAGAIN) \ |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 330 | schedule(); \ |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 331 | } while (err == -EAGAIN); \ |
| 332 | return err >= 0 ? err : 0; \ |
| 333 | } \ |
| 334 | static int mtk_serial##port##_tstc(void) \ |
| 335 | { \ |
| 336 | return _mtk_serial_pending(&mtk_hsuart##port, true); \ |
| 337 | } \ |
| 338 | static void mtk_serial##port##_putc(const char c) \ |
| 339 | { \ |
| 340 | int err; \ |
| 341 | if (c == '\n') \ |
| 342 | mtk_serial##port##_putc('\r'); \ |
| 343 | do { \ |
| 344 | err = _mtk_serial_putc(&mtk_hsuart##port, c); \ |
| 345 | } while (err == -EAGAIN); \ |
| 346 | } \ |
| 347 | static void mtk_serial##port##_puts(const char *s) \ |
| 348 | { \ |
| 349 | while (*s) { \ |
| 350 | mtk_serial##port##_putc(*s++); \ |
| 351 | } \ |
| 352 | } |
| 353 | |
| 354 | /* Serial device descriptor */ |
| 355 | #define INIT_HSUART_STRUCTURE(port, __name) { \ |
| 356 | .name = __name, \ |
| 357 | .start = mtk_serial##port##_init, \ |
| 358 | .stop = NULL, \ |
| 359 | .setbrg = mtk_serial##port##_setbrg, \ |
| 360 | .getc = mtk_serial##port##_getc, \ |
| 361 | .tstc = mtk_serial##port##_tstc, \ |
| 362 | .putc = mtk_serial##port##_putc, \ |
| 363 | .puts = mtk_serial##port##_puts, \ |
| 364 | } |
| 365 | |
| 366 | #define DECLARE_HSUART(port, __name) \ |
| 367 | DECLARE_HSUART_PRIV(port); \ |
| 368 | DECLARE_HSUART_FUNCTIONS(port); \ |
| 369 | struct serial_device mtk_hsuart##port##_device = \ |
| 370 | INIT_HSUART_STRUCTURE(port, __name); |
| 371 | |
| 372 | #if !defined(CONFIG_CONS_INDEX) |
| 373 | #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6) |
| 374 | #error "Invalid console index value." |
| 375 | #endif |
| 376 | |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 377 | #if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 378 | #error "Console port 1 defined but not configured." |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 379 | #elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 380 | #error "Console port 2 defined but not configured." |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 381 | #elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 382 | #error "Console port 3 defined but not configured." |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 383 | #elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 384 | #error "Console port 4 defined but not configured." |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 385 | #elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 386 | #error "Console port 5 defined but not configured." |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 387 | #elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 388 | #error "Console port 6 defined but not configured." |
| 389 | #endif |
| 390 | |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 391 | #if defined(CFG_SYS_NS16550_COM1) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 392 | DECLARE_HSUART(1, "mtk-hsuart0"); |
| 393 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 394 | #if defined(CFG_SYS_NS16550_COM2) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 395 | DECLARE_HSUART(2, "mtk-hsuart1"); |
| 396 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 397 | #if defined(CFG_SYS_NS16550_COM3) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 398 | DECLARE_HSUART(3, "mtk-hsuart2"); |
| 399 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 400 | #if defined(CFG_SYS_NS16550_COM4) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 401 | DECLARE_HSUART(4, "mtk-hsuart3"); |
| 402 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 403 | #if defined(CFG_SYS_NS16550_COM5) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 404 | DECLARE_HSUART(5, "mtk-hsuart4"); |
| 405 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 406 | #if defined(CFG_SYS_NS16550_COM6) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 407 | DECLARE_HSUART(6, "mtk-hsuart5"); |
| 408 | #endif |
| 409 | |
| 410 | __weak struct serial_device *default_serial_console(void) |
| 411 | { |
| 412 | #if CONFIG_CONS_INDEX == 1 |
| 413 | return &mtk_hsuart1_device; |
| 414 | #elif CONFIG_CONS_INDEX == 2 |
| 415 | return &mtk_hsuart2_device; |
| 416 | #elif CONFIG_CONS_INDEX == 3 |
| 417 | return &mtk_hsuart3_device; |
| 418 | #elif CONFIG_CONS_INDEX == 4 |
| 419 | return &mtk_hsuart4_device; |
| 420 | #elif CONFIG_CONS_INDEX == 5 |
| 421 | return &mtk_hsuart5_device; |
| 422 | #elif CONFIG_CONS_INDEX == 6 |
| 423 | return &mtk_hsuart6_device; |
| 424 | #else |
| 425 | #error "Bad CONFIG_CONS_INDEX." |
| 426 | #endif |
| 427 | } |
| 428 | |
| 429 | void mtk_serial_initialize(void) |
| 430 | { |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 431 | #if defined(CFG_SYS_NS16550_COM1) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 432 | serial_register(&mtk_hsuart1_device); |
| 433 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 434 | #if defined(CFG_SYS_NS16550_COM2) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 435 | serial_register(&mtk_hsuart2_device); |
| 436 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 437 | #if defined(CFG_SYS_NS16550_COM3) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 438 | serial_register(&mtk_hsuart3_device); |
| 439 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 440 | #if defined(CFG_SYS_NS16550_COM4) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 441 | serial_register(&mtk_hsuart4_device); |
| 442 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 443 | #if defined(CFG_SYS_NS16550_COM5) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 444 | serial_register(&mtk_hsuart5_device); |
| 445 | #endif |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 446 | #if defined(CFG_SYS_NS16550_COM6) |
developer | 77c7c73 | 2019-09-25 17:45:18 +0800 | [diff] [blame] | 447 | serial_register(&mtk_hsuart6_device); |
| 448 | #endif |
| 449 | } |
| 450 | |
| 451 | #endif |
| 452 | |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 453 | #ifdef CONFIG_DEBUG_UART_MTK |
| 454 | |
| 455 | #include <debug_uart.h> |
| 456 | |
| 457 | static inline void _debug_uart_init(void) |
| 458 | { |
| 459 | struct mtk_serial_priv priv; |
| 460 | |
developer | 5a83d2b | 2023-07-19 17:16:07 +0800 | [diff] [blame] | 461 | memset(&priv, 0, sizeof(struct mtk_serial_priv)); |
Pali Rohár | 8864b35 | 2022-05-27 22:15:24 +0200 | [diff] [blame] | 462 | priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 463 | priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK; |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 464 | |
| 465 | writel(0, &priv.regs->ier); |
developer | 67d2b61 | 2019-09-25 17:45:17 +0800 | [diff] [blame] | 466 | writel(UART_MCRVAL, &priv.regs->mcr); |
| 467 | writel(UART_FCRVAL, &priv.regs->fcr); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 468 | |
developer | 0dc720a | 2022-09-09 19:59:31 +0800 | [diff] [blame] | 469 | _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE, priv.fixed_clk_rate); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | static inline void _debug_uart_putc(int ch) |
| 473 | { |
| 474 | struct mtk_serial_regs __iomem *regs = |
Pali Rohár | 8864b35 | 2022-05-27 22:15:24 +0200 | [diff] [blame] | 475 | (void *) CONFIG_VAL(DEBUG_UART_BASE); |
developer | 90af58f | 2018-11-15 10:08:02 +0800 | [diff] [blame] | 476 | |
| 477 | while (!(readl(®s->lsr) & UART_LSR_THRE)) |
| 478 | ; |
| 479 | |
| 480 | writel(ch, ®s->thr); |
| 481 | } |
| 482 | |
| 483 | DEBUG_UART_FUNCS |
| 484 | |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 485 | #endif |