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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +01002/*
3 * Copyright (C) 2004-2007 ARM Limited.
4 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Michal Simekb3cc2602016-02-23 10:02:28 +01005 * Copyright (C) 2015 - 2016 Xilinx, Inc, Michal Simek
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +01006 *
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +01007 * As a special exception, if other files instantiate templates or use macros
8 * or inline functions from this file, or you compile this file and link it
9 * with other works to produce a work based on this file, this file does not
10 * by itself cause the resulting work to be covered by the GNU General Public
11 * License. However the source code for this file must still be made available
12 * in accordance with section (3) of the GNU General Public License.
13
14 * This exception does not invalidate any other reasons why a work based on
15 * this file might be covered by the GNU General Public License.
16 */
17
Michal Simekb3cc2602016-02-23 10:02:28 +010018#include <dm.h>
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +053019#include <serial.h>
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010020
Lokesh Vutlae3cb5142018-08-16 18:43:56 +053021#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7A) || defined(CONFIG_CPU_V7R)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010022/*
Alexander Merkle79bb2f62015-03-19 18:37:19 +010023 * ARMV6 & ARMV7
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010024 */
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020025#define DCC_RBIT (1 << 30)
26#define DCC_WBIT (1 << 29)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010027
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020028#define write_dcc(x) \
29 __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010030
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020031#define read_dcc(x) \
32 __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010033
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020034#define status_dcc(x) \
35 __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010036
Jean-Christophe PLAGNIOL-VILLARD195bb7c2009-05-15 23:47:14 +020037#elif defined(CONFIG_CPU_XSCALE)
38/*
39 * XSCALE
40 */
41#define DCC_RBIT (1 << 31)
42#define DCC_WBIT (1 << 28)
43
44#define write_dcc(x) \
45 __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
46
47#define read_dcc(x) \
48 __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
49
50#define status_dcc(x) \
51 __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
52
Tom Rini2d6f2192021-12-17 18:08:39 -050053#elif defined(CONFIG_ARM64)
Siva Durga Prasad Paladugu6d4b78b2015-05-29 09:54:37 +020054/*
55 * ARMV8
56 */
57#define DCC_RBIT (1 << 30)
58#define DCC_WBIT (1 << 29)
59
60#define write_dcc(x) \
61 __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x))
62
63#define read_dcc(x) \
64 __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x))
65
66#define status_dcc(x) \
67 __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x))
68
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020069#else
70#define DCC_RBIT (1 << 0)
71#define DCC_WBIT (1 << 1)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010072
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020073#define write_dcc(x) \
74 __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010075
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020076#define read_dcc(x) \
77 __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010078
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020079#define status_dcc(x) \
80 __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
81
82#endif
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010083
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020084#define can_read_dcc(x) do { \
85 status_dcc(x); \
86 x &= DCC_RBIT; \
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010087 } while (0);
88
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020089#define can_write_dcc(x) do { \
90 status_dcc(x); \
91 x &= DCC_WBIT; \
92 x = (x == 0); \
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010093 } while (0);
94
95#define TIMEOUT_COUNT 0x4000000
96
Michal Simekb3cc2602016-02-23 10:02:28 +010097static int arm_dcc_getc(struct udevice *dev)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010098{
99 int ch;
100 register unsigned int reg;
101
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200102 do {
103 can_read_dcc(reg);
104 } while (!reg);
105 read_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100106
107 return ch;
108}
109
Michal Simekb3cc2602016-02-23 10:02:28 +0100110static int arm_dcc_putc(struct udevice *dev, char ch)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100111{
112 register unsigned int reg;
113 unsigned int timeout_count = TIMEOUT_COUNT;
114
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200115 while (--timeout_count) {
116 can_write_dcc(reg);
117 if (reg)
118 break;
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100119 }
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200120 if (timeout_count == 0)
Michal Simekb3cc2602016-02-23 10:02:28 +0100121 return -EAGAIN;
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200122 else
123 write_dcc(ch);
Michal Simekb3cc2602016-02-23 10:02:28 +0100124
125 return 0;
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100126}
127
Michal Simekb3cc2602016-02-23 10:02:28 +0100128static int arm_dcc_pending(struct udevice *dev, bool input)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100129{
130 register unsigned int reg;
131
Michal Simekb3cc2602016-02-23 10:02:28 +0100132 if (input) {
133 can_read_dcc(reg);
134 } else {
135 can_write_dcc(reg);
136 }
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100137
138 return reg;
139}
140
Michal Simekb3cc2602016-02-23 10:02:28 +0100141static const struct dm_serial_ops arm_dcc_ops = {
142 .putc = arm_dcc_putc,
143 .pending = arm_dcc_pending,
144 .getc = arm_dcc_getc,
145};
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530146
Michal Simekb3cc2602016-02-23 10:02:28 +0100147static const struct udevice_id arm_dcc_ids[] = {
148 { .compatible = "arm,dcc", },
149 { }
150};
151
152U_BOOT_DRIVER(serial_dcc) = {
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530153 .name = "arm_dcc",
Michal Simekb3cc2602016-02-23 10:02:28 +0100154 .id = UCLASS_SERIAL,
155 .of_match = arm_dcc_ids,
156 .ops = &arm_dcc_ops,
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530157};
158
Michal Simekb3cc2602016-02-23 10:02:28 +0100159#ifdef CONFIG_DEBUG_UART_ARM_DCC
160
161#include <debug_uart.h>
162
163static inline void _debug_uart_init(void)
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530164{
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530165}
166
Michal Simekb3cc2602016-02-23 10:02:28 +0100167static inline void _debug_uart_putc(int ch)
Michal Simek0828cf22013-01-22 23:40:06 +0000168{
Michal Simekb3cc2602016-02-23 10:02:28 +0100169 arm_dcc_putc(NULL, ch);
Michal Simek0828cf22013-01-22 23:40:06 +0000170}
Michal Simekb3cc2602016-02-23 10:02:28 +0100171
172DEBUG_UART_FUNCS
173#endif