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git01.mediatek.com / filogic / uboot / 413c7b300d534f242ae6562f4728f028520f203e / . / drivers / clk / sunxi / clk_d1.c
blob: b990a1185948e320a1dd05d8e7a02cff80b33fee [file] [log] [blame]
Samuel Holland934d0f52022-04-30 22:38:37 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
4 */
5
Samuel Holland934d0f52022-04-30 22:38:37 -0500[diff] [blame]6#include <clk-uclass.h>
7#include <dm.h>
8#include <errno.h>
9#include <clk/sunxi.h>
10#include <dt-bindings/clock/sun20i-d1-ccu.h>
11#include <dt-bindings/reset/sun20i-d1-ccu.h>
12#include <linux/bitops.h>
13
14static struct ccu_clk_gate d1_gates[] = {
15 [CLK_APB0] = GATE_DUMMY,
16
17 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
18 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
19 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
20 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
23 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
24 [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
25 [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
26 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
27 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
28 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
29 [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
30 [CLK_SPI0] = GATE(0x940, BIT(31)),
31 [CLK_SPI1] = GATE(0x944, BIT(31)),
32 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
33 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
34
35 [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
36
37 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
38 [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
39 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
40 [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
41 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
42 [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
43 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
44 [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
45
46 [CLK_RISCV] = GATE(0xd04, BIT(31)),
47};
48
49static struct ccu_reset d1_resets[] = {
50 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
51 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
52 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
53 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
54 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
55 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
56 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
57 [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
58 [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
59 [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
60 [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
61 [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
62 [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
63 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
64 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
65
66 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
67
68 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
69 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
70 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
71 [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
72 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
73 [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
74 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
75 [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
76};
77
78const struct ccu_desc d1_ccu_desc = {
79 .gates = d1_gates,
80 .resets = d1_resets,
81 .num_gates = ARRAY_SIZE(d1_gates),
82 .num_resets = ARRAY_SIZE(d1_resets),
83};