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git01.mediatek.com / filogic / uboot / 413c7b300d534f242ae6562f4728f028520f203e / . / drivers / clk / adi / clk-adi-sc57x.c
blob: b17563f0444fe1962afbe4567172b0aa6e127baf [file] [log] [blame]
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * (C) Copyright 2022 - Analog Devices, Inc.
4 *
5 * Written and/or maintained by Timesys Corporation
6 *
7 * Author: Greg Malysa <greg.malysa@timesys.com>
8 *
9 * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
10 */
11
12#include <clk.h>
13#include <clk-uclass.h>
14#include <dm.h>
15#include <dt-bindings/clock/adi-sc5xx-clock.h>
16#include <linux/compiler_types.h>
17#include <linux/clk-provider.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/printk.h>
21#include <linux/types.h>
22
23#include "clk.h"
24
25static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
26static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
27static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"};
28static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"};
29static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
30static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "oclk_0_half"};
31static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"};
32static const char * const gige_sels[] = {"sclk1_0", "sclk1_1", "cclk0_1", "oclk_0"};
33static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1",
34 "dclk_1"};
35
36static int sc57x_clock_probe(struct udevice *dev)
37{
38 void __iomem *cgu0;
39 void __iomem *cgu1;
40 void __iomem *cdu;
41 int ret;
42 struct resource res;
43
44 struct clk *clks[ADSP_SC57X_CLK_END];
45 struct clk dummy, clkin0, clkin1;
46
47 ret = dev_read_resource_byname(dev, "cgu0", &res);
48 if (ret)
49 return ret;
50 cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
51
52 ret = dev_read_resource_byname(dev, "cgu1", &res);
53 if (ret)
54 return ret;
55 cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
56
57 ret = dev_read_resource_byname(dev, "cdu", &res);
58 if (ret)
59 return ret;
60 cdu = devm_ioremap(dev, res.start, resource_size(&res));
61
62 // Input clock configuration
63 clk_get_by_name(dev, "dummy", &dummy);
64 clk_get_by_name(dev, "sys_clkin0", &clkin0);
65 clk_get_by_name(dev, "sys_clkin1", &clkin1);
66
67 clks[ADSP_SC57X_CLK_DUMMY] = &dummy;
68 clks[ADSP_SC57X_CLK_SYS_CLKIN0] = &clkin0;
69 clks[ADSP_SC57X_CLK_SYS_CLKIN1] = &clkin1;
70
71 clks[ADSP_SC57X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
72 2, CLK_SET_RATE_PARENT,
73 cdu + CDU_CLKINSEL, 0, 1, 0);
74
75 // CGU configuration and internal clocks
76 clks[ADSP_SC57X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
77 "sys_clkin0",
78 CLK_SET_RATE_PARENT,
79 cgu0 + CGU_CTL, 0, 1, 0);
80 clks[ADSP_SC57X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
81 "cgu1_in_sel",
82 CLK_SET_RATE_PARENT,
83 cgu1 + CGU_CTL, 0, 1, 0);
84
85 // VCO output == PLL output
86 clks[ADSP_SC57X_CLK_CGU0_PLLCLK] = sc5xx_cgu_pll("cgu0_pllclk", "cgu0_df",
87 cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
88 CGU_MSEL_WIDTH, 0, false);
89 clks[ADSP_SC57X_CLK_CGU1_PLLCLK] = sc5xx_cgu_pll("cgu1_pllclk", "cgu1_df",
90 cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
91 CGU_MSEL_WIDTH, 0, false);
92
93 // Dividers from pll output
94 clks[ADSP_SC57X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
95 cgu0 + CGU_DIV, 0, 5, 0);
96 clks[ADSP_SC57X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
97 cgu0 + CGU_DIV, 8, 5, 0);
98 clks[ADSP_SC57X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
99 cgu0 + CGU_DIV, 16, 5, 0);
100 clks[ADSP_SC57X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
101 cgu0 + CGU_DIV, 22, 7, 0);
102 clks[ADSP_SC57X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
103 cgu0 + CGU_DIV, 5, 3, 0);
104 clks[ADSP_SC57X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
105 cgu0 + CGU_DIV, 13, 3, 0);
106
107 clks[ADSP_SC57X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
108 cgu1 + CGU_DIV, 0, 5, 0);
109 clks[ADSP_SC57X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
110 cgu1 + CGU_DIV, 8, 5, 0);
111 clks[ADSP_SC57X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
112 cgu1 + CGU_DIV, 16, 5, 0);
113 clks[ADSP_SC57X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
114 cgu1 + CGU_DIV, 22, 7, 0);
115 clks[ADSP_SC57X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv",
116 "sysclk_1", cgu1 + CGU_DIV, 5,
117 3, 0);
118 clks[ADSP_SC57X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv",
119 "sysclk_1", cgu1 + CGU_DIV, 13,
120 3, 0);
121
122 // Gates to enable CGU outputs
123 clks[ADSP_SC57X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
124 cgu0 + CGU_CCBF_DIS, 0);
125 clks[ADSP_SC57X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv",
126 cgu1 + CGU_CCBF_DIS, 1);
127 clks[ADSP_SC57X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
128 cgu0 + CGU_SCBF_DIS, 3);
129 clks[ADSP_SC57X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
130 cgu0 + CGU_SCBF_DIS, 2);
131 clks[ADSP_SC57X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv",
132 cgu0 + CGU_SCBF_DIS, 1);
133 clks[ADSP_SC57X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
134 cgu0 + CGU_SCBF_DIS, 0);
135
136 clks[ADSP_SC57X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
137 cgu1 + CGU_CCBF_DIS, 0);
138 clks[ADSP_SC57X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv",
139 cgu1 + CGU_CCBF_DIS, 1);
140 clks[ADSP_SC57X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
141 cgu1 + CGU_SCBF_DIS, 3);
142 clks[ADSP_SC57X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
143 cgu1 + CGU_SCBF_DIS, 2);
144 clks[ADSP_SC57X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv",
145 cgu1 + CGU_SCBF_DIS, 1);
146 clks[ADSP_SC57X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv",
147 cgu1 + CGU_SCBF_DIS, 0);
148
149 // Extra half rate clocks generated in the CDU
150 clks[ADSP_SC57X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half",
151 "oclk_0",
152 CLK_SET_RATE_PARENT,
153 1, 2);
154 clks[ADSP_SC57X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL,
155 "cclk1_1_half",
156 "cclk1_1",
157 CLK_SET_RATE_PARENT,
158 1, 2);
159
160 // CDU output muxes
161 clks[ADSP_SC57X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
162 sharc0_sels);
163 clks[ADSP_SC57X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
164 sharc1_sels);
165 clks[ADSP_SC57X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
166 clks[ADSP_SC57X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
167 cdu_ddr_sels);
168 clks[ADSP_SC57X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
169 clks[ADSP_SC57X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
170 clks[ADSP_SC57X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
171 clks[ADSP_SC57X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels);
172
173 // CDU output enable gates
174 clks[ADSP_SC57X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0,
175 CLK_IS_CRITICAL);
176 clks[ADSP_SC57X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1,
177 CLK_IS_CRITICAL);
178 clks[ADSP_SC57X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
179 CLK_IS_CRITICAL);
180 clks[ADSP_SC57X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3,
181 CLK_IS_CRITICAL);
182 clks[ADSP_SC57X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
183 clks[ADSP_SC57X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
184 clks[ADSP_SC57X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
185 clks[ADSP_SC57X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0);
186
187 ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
188 if (ret)
189 pr_err("CDU error detected\n");
190
191 return ret;
192}
193
194static const struct udevice_id adi_sc57x_clk_ids[] = {
195 { .compatible = "adi,sc57x-clocks" },
196 { },
197};
198
199U_BOOT_DRIVER(adi_sc57x_clk) = {
200 .name = "clk_adi_sc57x",
201 .id = UCLASS_CLK,
202 .of_match = adi_sc57x_clk_ids,
203 .ops = &adi_clk_ops,
204 .probe = sc57x_clock_probe,
205 .flags = DM_FLAG_PRE_RELOC,
206};