blob: 839ff4d2bf219dfd3053f2026e27676f16b00eb3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass4a56f102015-01-27 22:13:47 -07002/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Simon Glass4a56f102015-01-27 22:13:47 -07004 */
5
Simon Glassda25eff2019-12-28 10:44:56 -07006#include <init.h>
Simon Glass4a56f102015-01-27 22:13:47 -07007#include <mmc.h>
8#include <pci_ids.h>
Bin Meng947391c2015-07-30 03:49:18 -07009#include <asm/irq.h>
Bin Mengdc597802015-10-11 21:37:43 -070010#include <asm/mrccache.h>
Simon Glass4a56f102015-01-27 22:13:47 -070011#include <asm/post.h>
Bin Mengb11494c2017-10-12 05:07:57 -070012#include <asm/arch/iomap.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060013#include <asm/u-boot-x86.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Bin Mengb11494c2017-10-12 05:07:57 -070015
16/* GPIO SUS */
17#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
18#define GPIO_SUS_DFX5_CONF0 0x150
19#define BYT_TRIG_LVL BIT(24)
20#define BYT_TRIG_POS BIT(25)
Simon Glass4a56f102015-01-27 22:13:47 -070021
Simon Glass4a56f102015-01-27 22:13:47 -070022int arch_cpu_init(void)
23{
Simon Glass4a56f102015-01-27 22:13:47 -070024 post_code(POST_CPU_INIT);
Simon Glass4a56f102015-01-27 22:13:47 -070025
Masahiro Yamada17103212016-09-06 22:17:36 +090026 return x86_cpu_init_f();
Simon Glass4a56f102015-01-27 22:13:47 -070027}
Bin Meng947391c2015-07-30 03:49:18 -070028
29int arch_misc_init(void)
30{
Simon Glass5cc82b82015-08-10 07:05:12 -060031 if (!ll_boot_init())
32 return 0;
Simon Glass888697a2015-08-10 07:05:10 -060033
Bin Mengdc597802015-10-11 21:37:43 -070034#ifdef CONFIG_ENABLE_MRC_CACHE
35 /*
36 * We intend not to check any return value here, as even MRC cache
37 * is not saved successfully, it is not a severe error that will
38 * prevent system from continuing to boot.
39 */
40 mrccache_save();
41#endif
42
Bin Mengb11494c2017-10-12 05:07:57 -070043 /*
44 * For some unknown reason, FSP (gold4) for BayTrail configures
45 * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
46 * This does not cause any issue when Linux kernel runs w/ or w/o
47 * the pinctrl driver for BayTrail. However this causes unstable
48 * S3 resume if the pinctrl driver is included in the kernel build.
49 * As this pin keeps generating interrupts during an S3 resume,
50 * and there is no IRQ requester in the kernel to handle it, the
51 * kernel seems to hang and does not continue resuming.
52 *
53 * Clear the mysterious interrupt bits for this pin.
54 */
55 clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
56 BYT_TRIG_LVL | BYT_TRIG_POS);
57
Simon Glass754f55e2016-01-19 21:32:26 -070058 return 0;
Bin Meng947391c2015-07-30 03:49:18 -070059}