blob: 640c1a32e41bc3bdf05f2963a6d8b9ce1d8134f0 [file] [log] [blame]
Angelo Dureghelloc6164c92019-03-13 21:46:41 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
4 */
5
6/ {
7 compatible = "fsl,mcf5282";
8
9 aliases {
10 serial0 = &uart0;
Angelo Durgehelloc6e17f92019-11-15 23:54:12 +010011 fec0 = &fec0;
Angelo Dureghelloc6164c92019-03-13 21:46:41 +010012 };
13
14 soc {
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 ipsbar: ipsbar@4000000 {
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges = <0x00000000 0x40000000 0x40000000>;
24 reg = <0x40000000 0x40000000>;
25
Angelo Dureghello0e812302023-06-24 23:38:55 +020026 wdog0: watchdog@140000 {
27 compatible = "fsl,mcf5282-wdt";
28 reg = <0x140000 0x10>;
29 status = "disabled";
30 };
31
Angelo Dureghelloc6164c92019-03-13 21:46:41 +010032 uart0: uart@200 {
33 compatible = "fsl,mcf-uart";
34 reg = <0x200 0x40>;
35 status = "disabled";
36 };
37
38 uart1: uart@240 {
39 compatible = "fsl,mcf-uart";
40 reg = <0x240 0x40>;
41 status = "disabled";
42 };
43
44 uart2: uart@280 {
45 compatible = "fsl,mcf-uart";
46 reg = <0x280 0x40>;
47 status = "disabled";
48 };
Angelo Durgehelloc6e17f92019-11-15 23:54:12 +010049
50 fec0: ethernet@1000 {
51 compatible = "fsl,mcf-fec";
52 reg = <0x1000 0x800>;
53 mii-base = <0>;
54 max-speed = <100>;
55 timeout-loop = <50000>;
56 status = "disabled";
57 };
Angelo Dureghellod768df12023-04-05 00:59:27 +020058
59 i2c0: i2c@300 {
60 compatible = "fsl-i2c";
61 #address-cells=<1>;
62 #size-cells=<0>;
63 cell-index = <0>;
64 reg = <0x300 0x14>;
65 clock-frequency = <100000>;
66 status = "disabled";
67 };
Angelo Dureghelloc6164c92019-03-13 21:46:41 +010068 };
69 };
70};