| Gilles Talis | 42a5635 | 2023-12-13 09:29:40 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2019, 2021 NXP |
| 4 | * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #include "imx8mp-u-boot.dtsi" |
| 8 | |
| 9 | / { |
| 10 | wdt-reboot { |
| 11 | compatible = "wdt-reboot"; |
| 12 | wdt = <&wdog1>; |
| 13 | bootph-pre-ram; |
| 14 | }; |
| 15 | firmware { |
| 16 | optee { |
| 17 | compatible = "linaro,optee-tz"; |
| 18 | method = "smc"; |
| 19 | }; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | &crypto { |
| 24 | bootph-pre-ram; |
| 25 | }; |
| 26 | |
| 27 | ðphy0 { |
| 28 | reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; |
| 29 | reset-delay-us = <15000>; |
| 30 | reset-post-delay-us = <100000>; |
| 31 | }; |
| 32 | |
| 33 | &fec { |
| 34 | phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; |
| 35 | phy-reset-duration = <15>; |
| 36 | phy-reset-post-delay = <100>; |
| 37 | }; |
| 38 | |
| 39 | &gpio1 { |
| 40 | bootph-pre-ram; |
| 41 | }; |
| 42 | |
| 43 | &gpio2 { |
| 44 | bootph-pre-ram; |
| 45 | }; |
| 46 | |
| 47 | &gpio3 { |
| 48 | bootph-pre-ram; |
| 49 | }; |
| 50 | |
| 51 | &gpio4 { |
| 52 | bootph-pre-ram; |
| 53 | }; |
| 54 | |
| 55 | &gpio5 { |
| 56 | bootph-pre-ram; |
| 57 | }; |
| 58 | |
| 59 | &i2c1 { |
| 60 | bootph-pre-ram; |
| 61 | }; |
| 62 | |
| 63 | &pinctrl_i2c1 { |
| 64 | bootph-pre-ram; |
| 65 | }; |
| 66 | |
| 67 | &pinctrl_pmic { |
| 68 | bootph-pre-ram; |
| 69 | }; |
| 70 | |
| 71 | &pinctrl_uart2 { |
| 72 | bootph-pre-ram; |
| 73 | }; |
| 74 | |
| 75 | &pinctrl_usdhc2_gpio { |
| 76 | bootph-pre-ram; |
| 77 | }; |
| 78 | |
| 79 | &pinctrl_usdhc2 { |
| 80 | bootph-pre-ram; |
| 81 | }; |
| 82 | |
| 83 | &pinctrl_usdhc3 { |
| 84 | bootph-pre-ram; |
| 85 | }; |
| 86 | |
| 87 | &pinctrl_wdog { |
| 88 | bootph-pre-ram; |
| 89 | }; |
| 90 | |
| 91 | &pmic { |
| 92 | bootph-pre-ram; |
| 93 | |
| 94 | regulators { |
| 95 | bootph-pre-ram; |
| 96 | }; |
| 97 | }; |
| 98 | |
| 99 | ®_usdhc2_vmmc { |
| 100 | u-boot,off-on-delay-us = <20000>; |
| 101 | }; |
| 102 | |
| 103 | ®_usdhc2_vmmc { |
| 104 | bootph-pre-ram; |
| 105 | }; |
| 106 | |
| 107 | &uart2 { |
| 108 | bootph-pre-ram; |
| 109 | }; |
| 110 | |
| 111 | &sec_jr0 { |
| 112 | bootph-pre-ram; |
| 113 | }; |
| 114 | |
| 115 | &sec_jr1 { |
| 116 | bootph-pre-ram; |
| 117 | }; |
| 118 | |
| 119 | &sec_jr2 { |
| 120 | bootph-pre-ram; |
| 121 | }; |
| 122 | |
| 123 | &usdhc1 { |
| 124 | bootph-pre-ram; |
| 125 | }; |
| 126 | |
| 127 | &usdhc2 { |
| 128 | bootph-pre-ram; |
| 129 | sd-uhs-sdr104; |
| 130 | sd-uhs-ddr50; |
| 131 | }; |
| 132 | |
| 133 | &usdhc3 { |
| 134 | bootph-pre-ram; |
| 135 | mmc-hs400-1_8v; |
| 136 | mmc-hs400-enhanced-strobe; |
| 137 | }; |
| 138 | |
| 139 | &wdog1 { |
| 140 | bootph-pre-ram; |
| 141 | }; |