blob: ccf665b211863a97fe4f0bb832e885f844cb69e9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07002/*
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +02003 * Copyright (c) 2016-2018 Toradex, Inc.
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07004 */
5
6#include <common.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +02007#include <dm.h>
Simon Glassed38aef2020-05-10 11:40:03 -06008#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070011#include <asm/arch-tegra/ap.h>
12#include <asm/gpio.h>
13#include <asm/io.h>
14#include <asm/arch/gpio.h>
15#include <asm/arch/pinmux.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060016#include <env_internal.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020017#include <pci_tegra.h>
Simon Glassdbd79542020-05-10 11:40:11 -060018#include <linux/delay.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070019#include <power/as3722.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020020#include <power/pmic.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070021
22#include "../common/tdx-common.h"
23#include "pinmux-config-apalis-tk1.h"
24
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020025#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
26#define LAN_RESET_N TEGRA_GPIO(S, 2)
Igor Opaniukfeb8c0d2019-08-01 11:06:32 +030027#define FAN_EN TEGRA_GPIO(DD, 2)
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020028#define LAN_WAKE_N TEGRA_GPIO(O, 5)
29#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
30#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
31#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
32#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
Marcel Ziswiler46eb7292019-08-09 13:21:46 +030033#define VCC_USBH TEGRA_GPIO(T, 6)
34#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5)
35#define VCC_USBO1 TEGRA_GPIO(T, 5)
36#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070037
38int arch_misc_init(void)
39{
40 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
Marcel Ziswiler55fb0572021-08-11 15:12:56 +020041 NVBOOTTYPE_RECOVERY) {
42 printf("USB recovery mode, attempting to boot Toradex Easy "
43 "Installer\n");
44 env_set("bootdelay", "-2");
45 env_set("defargs", "pcie_aspm=off user_debug=30");
46 env_set("fdt_high", "");
47 env_set("initrd_high", "");
48
49 env_set("setup", "env set setupargs igb_mac=${ethaddr} "
50 "consoleblank=0 no_console_suspend=1 "
51 "console=${console},${baudrate}n8 ${memargs}");
52 env_set("teziargs", "rootfstype=squashfs root=/dev/ram quiet "
53 "autoinstall");
54 env_set("vidargs", "video=HDMI-A-1:640x480-16@60D");
55 env_set("bootcmd", "run setup; env set bootargs ${defargs} "
56 "${setupargs} ${vidargs} ${teziargs}; bootm 0x80208000"
57 "#config@${soc}-${fdt_module}-${fdt_board}.dtb");
58 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070059
Marcel Ziswiler46eb7292019-08-09 13:21:46 +030060 /* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
61 gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
62 gpio_direction_input(TEGRA_GPIO(V, 0));
63 if (gpio_get_value(TEGRA_GPIO(V, 0))) {
64 /*
65 * if using the default device tree for new V1.2 and later HW,
66 * use version for older V1.0 and V1.1 HW
67 */
68 char *fdt_env = env_get("fdt_module");
69
70 if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
71 env_set("fdt_module", FDT_MODULE_V1_0);
72 printf("patching fdt_module to " FDT_MODULE_V1_0
73 " for older V1.0 and V1.1 HW\n");
Marcel Ziswiler46eb7292019-08-09 13:21:46 +030074 }
75
76 /* activate USB power enable GPIOs */
77 gpio_request(VCC_USBH_V1_0, "VCC_USBH");
78 gpio_direction_output(VCC_USBH_V1_0, 1);
79 gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
80 gpio_direction_output(VCC_USBO1_V1_0, 1);
81 } else {
82 /* activate USB power enable GPIOs */
83 gpio_request(VCC_USBH, "VCC_USBH");
84 gpio_direction_output(VCC_USBH, 1);
85 gpio_request(VCC_USBO1, "VCC_USBO1");
86 gpio_direction_output(VCC_USBO1, 1);
87 }
88
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070089 return 0;
90}
91
92int checkboard(void)
93{
94 puts("Model: Toradex Apalis TK1 2GB\n");
95
96 return 0;
97}
98
99#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900100int ft_board_setup(void *blob, struct bd_info *bd)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700101{
102 return ft_common_board_setup(blob, bd);
103}
104#endif
105
106/*
107 * Routine: pinmux_init
108 * Description: Do individual peripheral pinmux configs
109 */
110void pinmux_init(void)
111{
112 pinmux_clear_tristate_input_clamping();
113
114 gpio_config_table(apalis_tk1_gpio_inits,
115 ARRAY_SIZE(apalis_tk1_gpio_inits));
116
117 pinmux_config_pingrp_table(apalis_tk1_pingrps,
118 ARRAY_SIZE(apalis_tk1_pingrps));
119
120 pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
121 ARRAY_SIZE(apalis_tk1_drvgrps));
122}
123
124#ifdef CONFIG_PCI_TEGRA
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200125/* TODO: Convert to driver model */
126static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700127{
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700128 int err;
129
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200130 if (sd > 6)
131 return -EINVAL;
132
133 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700134 if (err) {
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200135 pr_err("failed to update SD control register: %d", err);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700136 return err;
137 }
138
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200139 return 0;
140}
141
142/* TODO: Convert to driver model */
143static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
144{
145 int err;
146 u8 ctrl_reg = AS3722_LDO_CONTROL0;
147
148 if (ldo > 11)
149 return -EINVAL;
150
151 if (ldo > 7) {
152 ctrl_reg = AS3722_LDO_CONTROL1;
153 ldo -= 8;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700154 }
155
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200156 err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
157 if (err) {
158 pr_err("failed to update LDO control register: %d", err);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700159 return err;
160 }
161
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200162 return 0;
163}
164
165int tegra_pcie_board_init(void)
166{
167 struct udevice *dev;
168 int ret;
169
170 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Simon Glass65130cd2020-12-28 20:34:56 -0700171 DM_DRIVER_GET(pmic_as3722), &dev);
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200172 if (ret) {
173 pr_err("failed to find AS3722 PMIC: %d\n", ret);
174 return ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700175 }
176
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200177 ret = as3722_sd_enable(dev, 4);
178 if (ret < 0) {
179 pr_err("failed to enable SD4: %d\n", ret);
180 return ret;
181 }
182
183 ret = as3722_sd_set_voltage(dev, 4, 0x24);
184 if (ret < 0) {
185 pr_err("failed to set SD4 voltage: %d\n", ret);
186 return ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700187 }
188
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200189 gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700190 gpio_request(LAN_RESET_N, "LAN_RESET_N");
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200191 gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
192
193#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
194 gpio_request(PEX_PERST_N, "PEX_PERST_N");
195 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
196#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700197
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200198 return 0;
199}
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700200
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200201void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
202{
203 int index = tegra_pcie_port_index_of_port(port);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700204
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200205 if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
206 struct udevice *dev;
207 int ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700208
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200209 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Simon Glass65130cd2020-12-28 20:34:56 -0700210 DM_DRIVER_GET(pmic_as3722),
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200211 &dev);
212 if (ret) {
213 debug("%s: Failed to find PMIC\n", __func__);
214 return;
215 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700216
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200217 /* Reset I210 Gigabit Ethernet Controller */
218 gpio_direction_output(LAN_RESET_N, 0);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700219
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200220 /*
221 * Make sure we don't get any back feeding from DEV_OFF_N resp.
222 * LAN_WAKE_N
223 */
224 gpio_direction_output(LAN_DEV_OFF_N, 0);
225 gpio_direction_output(LAN_WAKE_N, 0);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700226
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200227 /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
228 ret = as3722_ldo_enable(dev, 9);
229 if (ret < 0) {
230 pr_err("failed to enable LDO9: %d\n", ret);
231 return;
232 }
233 ret = as3722_ldo_enable(dev, 10);
234 if (ret < 0) {
235 pr_err("failed to enable LDO10: %d\n", ret);
236 return;
237 }
238 ret = as3722_ldo_set_voltage(dev, 9, 0x80);
239 if (ret < 0) {
240 pr_err("failed to set LDO9 voltage: %d\n", ret);
241 return;
242 }
243 ret = as3722_ldo_set_voltage(dev, 10, 0x80);
244 if (ret < 0) {
245 pr_err("failed to set LDO10 voltage: %d\n", ret);
246 return;
247 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700248
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200249 /* Make sure controller gets enabled by disabling DEV_OFF_N */
250 gpio_set_value(LAN_DEV_OFF_N, 1);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700251
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200252 /*
253 * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
254 * V1.0A and sample V1.0B and newer modules
255 */
256 ret = as3722_ldo_set_voltage(dev, 9, 0xff);
257 if (ret < 0) {
258 pr_err("failed to set LDO9 voltage: %d\n", ret);
259 return;
260 }
261 ret = as3722_ldo_set_voltage(dev, 10, 0xff);
262 if (ret < 0) {
263 pr_err("failed to set LDO10 voltage: %d\n", ret);
264 return;
265 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700266
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200267 /*
268 * Must be asserted for 100 ms after power and clocks are stable
269 */
270 mdelay(100);
271
272 gpio_set_value(LAN_RESET_N, 1);
273 } else if (index == 0) { /* Apalis PCIe */
274#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
275 /*
276 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
277 * Evaluation Board
278 */
279 gpio_direction_output(PEX_PERST_N, 0);
280 gpio_direction_output(RESET_MOCI_CTRL, 0);
281
282 /*
283 * Must be asserted for 100 ms after power and clocks are stable
284 */
285 mdelay(100);
286
287 gpio_set_value(PEX_PERST_N, 1);
288 /*
289 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
290 * Until 900 us After PEX_PERST# De-assertion
291 */
292 mdelay(1);
293 gpio_set_value(RESET_MOCI_CTRL, 1);
294#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
295 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700296}
297#endif /* CONFIG_PCI_TEGRA */
Gerard Salvatella108d7392018-11-19 15:54:10 +0100298
299/*
Igor Opaniukfeb8c0d2019-08-01 11:06:32 +0300300 * Enable/start PWM CPU fan
301 */
302void start_cpu_fan(void)
303{
304 gpio_request(FAN_EN, "FAN_EN");
305 gpio_direction_output(FAN_EN, 1);
306}
307
308/*
Gerard Salvatella108d7392018-11-19 15:54:10 +0100309 * Backlight off before OS handover
310 */
311void board_preboot_os(void)
312{
313 gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
314 gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
315}