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git01.mediatek.com / filogic / uboot / 41372ad8e4def36c4798d76915e27325b087a5c3 / . / board / ep82xxm / ep82xxm.c
blob: 182cabca148124598e131e70c5c9266760e4df7d [file] [log] [blame]
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]1/*
2 * Copyright (C) 2006 Embedded Planet, LLC.
3 *
4 * Support for Embedded Planet EP82xxM boards.
5 * Tested on EP82xxM (MPC8270).
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <mpc8260.h>
28#include <ioports.h>
29#include <asm/m8260_pci.h>
30#ifdef CONFIG_PCI
31#include <pci.h>
32#endif
33#include <miiphy.h>
Wolfgang Denk41372ad2011-11-05 05:13:09 +0000[diff] [blame^]34#include <linux/compiler.h>
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]35
36/*
37 * I/O Port configuration table
38 *
39 * if conf is 1, then that port pin will be configured at boot time
40 * according to the five values podr/pdir/ppar/psor/pdat for that entry
41 */
42
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]43#define CONFIG_SYS_FCC2 1
44#define CONFIG_SYS_FCC3 1
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]45
46const iop_conf_t iop_conf_tab[4][32] = {
47
48 /* Port A */
49 { /* conf ppar psor pdir podr pdat */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]50 /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */
51 /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */
52 /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */
53 /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */
54 /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */
55 /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */
56 /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */
57 /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */
58 /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */
59 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
60 /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */
61 /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */
62 /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */
63 /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */
64 /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */
65 /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */
66 /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */
67 /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */
68 /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */
69 /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */
70 /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */
71 /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */
72 /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */
73 /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */
74 /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */
75 /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */
76 /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */
77 /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */
78 /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */
79 /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */
80 /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */
81 /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]82 },
83
84 /* Port B */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]85 { /* conf ppar psor pdir podr pdat */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]86 /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
87 /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
88 /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
89 /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
90 /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
91 /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
92 /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
93 /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
94 /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
95 /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
96 /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
97 /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
98 /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
99 /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
100 /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
101 /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
102 /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
103 /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
104 /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
105 /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
106 /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
107 /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
108 /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
109 /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]110 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]111 /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
112 /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
113 /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]114 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
115 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
116 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
117 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]118 },
119
120 /* Port C */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]121 { /* conf ppar psor pdir podr pdat */
122 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
123 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
124 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */
125 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]126 /* PC27 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]127 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
128 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
129 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
130 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
131 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
132 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
133 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]134 /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */
135 /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */
136 /* PC17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */
137 /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]138 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
139 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */
140 /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */
141 /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */
142 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
143 /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */
144 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
145 /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */
146 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
147 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
148 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
149 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
150 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
151 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
152 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
153 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]154 },
155
156 /* Port D */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]157 { /* conf ppar psor pdir podr pdat */
158 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
159 /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */
160 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */
161 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
162 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
163 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */
164 /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
165 /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */
166 /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */
167 /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */
168 /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */
169 /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */
170 /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */
171 /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */
172 /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */
173 /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */
174 /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */
175 /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */
176 /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */
177 /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */
178 /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */
179 /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */
180 /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */
181 /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */
182 /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */
183 /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */
184 /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */
185 /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */
186 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
187 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
188 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
189 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]190 }
191};
192
193#ifdef CONFIG_PCI
194typedef struct pci_ic_s {
195 unsigned long pci_int_stat;
196 unsigned long pci_int_mask;
197}pci_ic_t;
198#endif
199
200int board_early_init_f (void)
201{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]202 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]203
204 bcsr[4] |= 0x30; /* Turn the LEDs off */
205
206#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
207 bcsr[6] |= 0x10;
208#endif
209#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
210 bcsr[7] |= 0x10;
211#endif
212
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]213#if CONFIG_SYS_FCC3
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]214 bcsr[8] |= 0xC0;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]215#endif /* CONFIG_SYS_FCC3 */
216#if CONFIG_SYS_FCC2
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]217 bcsr[8] |= 0x30;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]218#endif /* CONFIG_SYS_FCC2 */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]219
220 return 0;
221}
222
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]223phys_size_t initdram(int board_type)
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]224{
225 /* Size in MB of SDRAM populated on board*/
226 long int msize = 256;
227
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]228#ifndef CONFIG_SYS_RAMBOOT
229 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]230 volatile memctl8260_t *memctl = &immap->im_memctl;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]231 uint psdmr = CONFIG_SYS_PSDMR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]232 int i;
233
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]234 unsigned char *ramptr1 = (unsigned char *)0x00000110;
Wolfgang Denk41372ad2011-11-05 05:13:09 +0000[diff] [blame^]235 __maybe_unused unsigned char ramtmp;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]236
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]237 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]238
239udelay(400);
240
241 /* Initialise 60x bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]242 memctl->memc_psrt = CONFIG_SYS_PSRT;
243 memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
244 memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]245 memctl->memc_psdmr = psdmr;
246
247udelay(400);
248
249 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
250 ramtmp = *ramptr1;
251 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
252 for (i = 0; i < 8; i++) {
253 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
254 }
255 ramtmp = *ramptr1;
256 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
257 *ramptr1 = 0xFF;
258 memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]259#endif /* !CONFIG_SYS_RAMBOOT */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]260
261 /* Return total 60x bus SDRAM size */
262 return msize * 1024 * 1024;
263}
264
265int checkboard(void)
266{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]267 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]268
269 puts("Board: ");
270 switch (bcsr[0]) {
271 case 0x0A:
272 printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
273 break;
274 default:
275 printf("unknown: ID=%02X\n", bcsr[0]);
276 }
277
278 return 0;
279}
280
281#ifdef CONFIG_PCI
282struct pci_controller hose;
283
284extern void pci_mpc8250_init(struct pci_controller *);
285
286void pci_init_board(void)
287{
288 pci_mpc8250_init(&hose);
289}
290#endif