Blame - arch/x86/cpu/broadwell/Kconfig - filogic/uboot

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Tom Rini	10e4779	2018-05-06 17:58:06 -0400	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0
Simon Glass	71606de	2016-03-11 22:07:18 -0700	[diff] [blame]	2	#
				3	# Copyright (C) 2016 Google Inc.
				4	#
Simon Glass	71606de	2016-03-11 22:07:18 -0700	[diff] [blame]	5
				6	config INTEL_BROADWELL
				7	bool
				8	select CACHE_MRC_BIN
Tom Rini	7d3684a	2023-01-16 15:46:49 -0500	[diff] [blame]	9	select DM_EVENT
Bin Meng	6f40e7c	2017-07-30 06:23:13 -0700	[diff] [blame]	10	select ARCH_EARLY_INIT_R
Bin Meng	d3935ff	2017-07-30 06:23:10 -0700	[diff] [blame]	11	imply HAVE_INTEL_ME
Bin Meng	1949a9a	2017-07-30 06:23:14 -0700	[diff] [blame]	12	imply ENABLE_MRC_CACHE
Bin Meng	73f5bc1	2017-07-30 19:24:02 -0700	[diff] [blame]	13	imply AHCI_PCI
Bin Meng	0120fef	2017-07-30 06:23:19 -0700	[diff] [blame]	14	imply ICH_SPI
				15	imply INTEL_BROADWELL_GPIO
				16	imply SCSI
Tuomas Tynkkynen	edf9f62	2017-12-08 15:36:19 +0200	[diff] [blame]	17	imply SCSI_AHCI
Bin Meng	0120fef	2017-07-30 06:23:19 -0700	[diff] [blame]	18	imply SPI_FLASH
Bin Meng	5b5d173	2017-07-30 06:23:27 -0700	[diff] [blame]	19	imply USB
				20	imply USB_EHCI_HCD
Bin Meng	0120fef	2017-07-30 06:23:19 -0700	[diff] [blame]	21	imply VIDEO_BROADWELL_IGD
Simon Glass	71606de	2016-03-11 22:07:18 -0700	[diff] [blame]	22
				23	if INTEL_BROADWELL
				24
				25	config DCACHE_RAM_BASE
				26	default 0xff7c0000
				27
				28	config DCACHE_RAM_SIZE
				29	default 0x40000
				30
				31	config DCACHE_RAM_MRC_VAR_SIZE
				32	default 0x30000
				33
				34	config CPU_SPECIFIC_OPTIONS
				35	def_bool y
				36	select SMM_TSEG
				37	select X86_RAMTEST
				38
				39	config SMM_TSEG_SIZE
				40	hex
				41	default 0x800000
				42
				43	endif