blob: ae7c18196894cacfee36ff0987ed0504fa2ed5f3 [file] [log] [blame]
Michal Simekc13291f2019-08-06 12:07:10 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU216
4 *
Michal Simek821e32a2021-05-31 09:50:01 +02005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
Michal Simekc13291f2019-08-06 12:07:10 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
Michal Simekf7b922a2021-05-10 13:14:02 +020016#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
Michal Simekc13291f2019-08-06 12:07:10 +020017#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP ZCU216 RevA";
21 compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp";
22
23 aliases {
24 ethernet0 = &gem3;
Michal Simekc13291f2019-08-06 12:07:10 +020025 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +020028 nvmem0 = &eeprom;
Michal Simekc13291f2019-08-06 12:07:10 +020029 rtc0 = &rtc;
30 serial0 = &uart0;
31 serial1 = &dcc;
32 spi0 = &qspi;
33 usb0 = &usb0;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simekc13291f2019-08-06 12:07:10 +020039 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 };
45
46 gpio-keys {
47 compatible = "gpio-keys";
48 autorepeat;
49 sw19 {
50 label = "sw19";
51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_DOWN>;
Michal Simekf701e192020-02-18 12:06:14 +010053 wakeup-source;
Michal Simekc13291f2019-08-06 12:07:10 +020054 autorepeat;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 heartbeat_led {
61 label = "heartbeat";
62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
64 };
65 };
66
67 ina226-vccint {
68 compatible = "iio-hwmon";
69 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
70 };
71 ina226-vccint-io-bram-ps {
72 compatible = "iio-hwmon";
73 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
74 };
75 ina226-vcc1v8 {
76 compatible = "iio-hwmon";
77 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
78 };
79 ina226-vcc1v2 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
82 };
83 ina226-vadj-fmc {
84 compatible = "iio-hwmon";
85 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
86 };
87 ina226-mgtavcc {
88 compatible = "iio-hwmon";
89 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
90 };
91 ina226-mgt1v2 {
92 compatible = "iio-hwmon";
93 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
94 };
95 ina226-mgt1v8 {
96 compatible = "iio-hwmon";
97 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
98 };
99 ina226-vccint-ams {
100 compatible = "iio-hwmon";
101 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
102 };
103 ina226-dac-avtt {
104 compatible = "iio-hwmon";
105 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
106 };
107 ina226-dac-avccaux {
108 compatible = "iio-hwmon";
109 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
110 };
111 ina226-adc-avcc {
112 compatible = "iio-hwmon";
113 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
114 };
115 ina226-adc-avccaux {
116 compatible = "iio-hwmon";
117 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
118 };
119 ina226-dac-avcc {
120 compatible = "iio-hwmon";
121 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
122 };
Michal Simek958c0e92020-11-26 14:25:02 +0100123
124 /* 48MHz reference crystal */
125 ref48: ref48M {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <48000000>;
129 };
130};
131
132&psgtr {
133 status = "okay";
Michal Simek9697c3b2021-05-31 09:56:58 +0200134 /* nc, nc, usb3, sata */
135 clocks = <&si5341 0 2>, <&si5341 0 3>;
136 clock-names = "ref2", "ref3";
Michal Simekc13291f2019-08-06 12:07:10 +0200137};
138
139&dcc {
140 status = "okay";
141};
142
143&fpd_dma_chan1 {
144 status = "okay";
145};
146
147&fpd_dma_chan2 {
148 status = "okay";
149};
150
151&fpd_dma_chan3 {
152 status = "okay";
153};
154
155&fpd_dma_chan4 {
156 status = "okay";
157};
158
159&fpd_dma_chan5 {
160 status = "okay";
161};
162
163&fpd_dma_chan6 {
164 status = "okay";
165};
166
167&fpd_dma_chan7 {
168 status = "okay";
169};
170
171&fpd_dma_chan8 {
172 status = "okay";
173};
174
175&gem3 {
176 status = "okay";
177 phy-handle = <&phy0>;
178 phy-mode = "rgmii-id";
179 phy0: ethernet-phy@c {
180 reg = <0xc>;
181 ti,rx-internal-delay = <0x8>;
182 ti,tx-internal-delay = <0xa>;
183 ti,fifo-depth = <0x1>;
184 ti,dp83867-rxctrl-strap-quirk;
185 };
186};
187
188&gpio {
189 status = "okay";
190 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
191 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
192 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
193 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
194 "", "", "BUTTON", "LED", "", /* 20 - 24 */
195 "", "PMU_INPUT", "", "", "", /* 25 - 29 */
196 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
197 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
198 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
199 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
200 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
201 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
202 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
203 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
204 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
205 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
206 "", "", /* 78 - 79 */
207 "", "", "", "", "", /* 80 - 84 */
208 "", "", "", "", "", /* 85 -89 */
209 "", "", "", "", "", /* 90 - 94 */
210 "", "", "", "", "", /* 95 - 99 */
211 "", "", "", "", "", /* 100 - 104 */
212 "", "", "", "", "", /* 105 - 109 */
213 "", "", "", "", "", /* 110 - 114 */
214 "", "", "", "", "", /* 115 - 119 */
215 "", "", "", "", "", /* 120 - 124 */
216 "", "", "", "", "", /* 125 - 129 */
217 "", "", "", "", "", /* 130 - 134 */
218 "", "", "", "", "", /* 135 - 139 */
219 "", "", "", "", "", /* 140 - 144 */
220 "", "", "", "", "", /* 145 - 149 */
221 "", "", "", "", "", /* 150 - 154 */
222 "", "", "", "", "", /* 155 - 159 */
223 "", "", "", "", "", /* 160 - 164 */
224 "", "", "", "", "", /* 165 - 169 */
225 "", "", "", ""; /* 170 - 174 */
226};
227
228&gpu {
229 status = "okay";
230};
231
232&i2c0 {
233 status = "okay";
234 clock-frequency = <400000>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200235 pinctrl-names = "default", "gpio";
236 pinctrl-0 = <&pinctrl_i2c0_default>;
237 pinctrl-1 = <&pinctrl_i2c0_gpio>;
238 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
239 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
Michal Simekc13291f2019-08-06 12:07:10 +0200240
241 tca6416_u15: gpio@20 { /* u15 */
242 compatible = "ti,tca6416";
243 reg = <0x20>;
244 gpio-controller; /* interrupt not connected */
245 #gpio-cells = <2>;
246 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */
247 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
248 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
249 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
250 };
251
252 i2c-mux@75 { /* u17 */
253 compatible = "nxp,pca9544";
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <0x75>;
257 i2c@0 {
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <0>;
261 /* PS_PMBUS */
262 /* PMBUS_ALERT done via pca9544 */
263 vccint: ina226@40 { /* u65 */
264 compatible = "ti,ina226";
265 #io-channel-cells = <1>;
266 label = "ina226-vccint";
267 reg = <0x40>;
268 shunt-resistor = <5000>;
269 };
270 vccint_io_bram_ps: ina226@41 { /* u57 */
271 compatible = "ti,ina226";
272 #io-channel-cells = <1>;
273 label = "ina226-vccint-io-bram-ps";
274 reg = <0x41>;
Michal Simek4cb602c2019-11-25 09:55:28 +0100275 shunt-resistor = <5000>;
Michal Simekc13291f2019-08-06 12:07:10 +0200276 };
277 vcc1v8: ina226@42 { /* u60 */
278 compatible = "ti,ina226";
279 #io-channel-cells = <1>;
280 label = "ina226-vcc1v8";
281 reg = <0x42>;
282 shunt-resistor = <2000>;
283 };
284 vcc1v2: ina226@43 { /* u58 */
285 compatible = "ti,ina226";
286 #io-channel-cells = <1>;
287 label = "ina226-vcc1v2";
288 reg = <0x43>;
289 shunt-resistor = <5000>;
290 };
291 vadj_fmc: ina226@45 { /* u62 */
292 compatible = "ti,ina226";
293 #io-channel-cells = <1>;
294 label = "ina226-vadj-fmc";
295 reg = <0x45>;
296 shunt-resistor = <5000>;
297 };
298 mgtavcc: ina226@46 { /* u67 */
299 compatible = "ti,ina226";
300 #io-channel-cells = <1>;
301 label = "ina226-mgtavcc";
302 reg = <0x46>;
303 shunt-resistor = <2000>;
304 };
305 mgt1v2: ina226@47 { /* u63 */
306 compatible = "ti,ina226";
307 #io-channel-cells = <1>;
308 label = "ina226-mgt1v2";
309 reg = <0x47>;
310 shunt-resistor = <5000>;
311 };
312 mgt1v8: ina226@48 { /* u64 */
313 compatible = "ti,ina226";
314 #io-channel-cells = <1>;
315 label = "ina226-mgt1v8";
316 reg = <0x48>;
317 shunt-resistor = <5000>;
318 };
319 vccint_ams: ina226@49 { /* u61 */
320 compatible = "ti,ina226";
321 #io-channel-cells = <1>;
322 label = "ina226-vccint-ams";
323 reg = <0x49>;
Michal Simek4cb602c2019-11-25 09:55:28 +0100324 shunt-resistor = <5000>;
Michal Simekc13291f2019-08-06 12:07:10 +0200325 };
326 dac_avtt: ina226@4a { /* u59 */
327 compatible = "ti,ina226";
328 #io-channel-cells = <1>;
329 label = "ina226-dac-avtt";
330 reg = <0x4a>;
331 shunt-resistor = <5000>;
332 };
333 dac_avccaux: ina226@4b { /* u124 */
334 compatible = "ti,ina226";
335 #io-channel-cells = <1>;
336 label = "ina226-dac-avccaux";
337 reg = <0x4b>;
338 shunt-resistor = <5000>;
339 };
340 adc_avcc: ina226@4c { /* u75 */
341 compatible = "ti,ina226";
342 #io-channel-cells = <1>;
343 label = "ina226-adc-avcc";
344 reg = <0x4c>;
345 shunt-resistor = <5000>;
346 };
347 adc_avccaux: ina226@4d { /* u71 */
348 compatible = "ti,ina226";
349 #io-channel-cells = <1>;
350 label = "ina226-adc-avccaux";
351 reg = <0x4d>;
352 shunt-resistor = <5000>;
353 };
354 dac_avcc: ina226@4e { /* u77 */
355 compatible = "ti,ina226";
356 #io-channel-cells = <1>;
357 label = "ina226-dac-avcc";
358 reg = <0x4e>;
359 shunt-resistor = <5000>;
360 };
361 };
362 i2c@1 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 reg = <1>;
366 /* NC */
367 };
368 i2c@2 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <2>;
372 /* u104 - ir35215 0x10/0x40 */
373 /* u127 - ir38164 0x1b/0x4b */
374 /* u112 - ir38164 0x13/0x43 */
375 /* u123 - ir38164 0x1c/0x4c */
376
Michal Simek3514e4e2020-03-30 11:35:38 +0200377 irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
Michal Simekc13291f2019-08-06 12:07:10 +0200378 compatible = "infineon,irps5401";
379 reg = <0x44>; /* i2c addr 0x14 */
380 };
Michal Simek3514e4e2020-03-30 11:35:38 +0200381 irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
Michal Simekc13291f2019-08-06 12:07:10 +0200382 compatible = "infineon,irps5401";
383 reg = <0x45>; /* i2c addr 0x15 */
384 };
385 /* J21 header too */
386
387 };
388 i2c@3 {
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <3>;
392 /* SYSMON */
393 };
394 };
395 /* u38 MPS430 */
396};
397
398&i2c1 {
399 status = "okay";
400 clock-frequency = <400000>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200401 pinctrl-names = "default", "gpio";
402 pinctrl-0 = <&pinctrl_i2c1_default>;
403 pinctrl-1 = <&pinctrl_i2c1_gpio>;
404 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
405 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
Michal Simekc13291f2019-08-06 12:07:10 +0200406
407 i2c-mux@74 {
408 compatible = "nxp,pca9548"; /* u20 */
409 #address-cells = <1>;
410 #size-cells = <0>;
411 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600412 i2c-mux-idle-disconnect;
Michal Simekc13291f2019-08-06 12:07:10 +0200413 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
414 i2c_eeprom: i2c@0 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 reg = <0>;
418 /*
419 * IIC_EEPROM 1kB memory which uses 256B blocks
420 * where every block has different address.
421 * 0 - 256B address 0x54
422 * 256B - 512B address 0x55
423 * 512B - 768B address 0x56
424 * 768B - 1024B address 0x57
425 */
426 eeprom: eeprom@54 { /* u21 */
Raviteja Narayanam856d52d2019-11-26 18:22:50 +0530427 compatible = "atmel,24c128";
Michal Simekc13291f2019-08-06 12:07:10 +0200428 reg = <0x54>;
429 };
430 };
431 i2c_si5341: i2c@1 {
432 #address-cells = <1>;
433 #size-cells = <0>;
434 reg = <1>;
435 si5341: clock-generator@36 { /* SI5341 - u43 */
Michal Simek958c0e92020-11-26 14:25:02 +0100436 compatible = "silabs,si5341";
Michal Simekc13291f2019-08-06 12:07:10 +0200437 reg = <0x36>;
Michal Simek958c0e92020-11-26 14:25:02 +0100438 #clock-cells = <2>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 clocks = <&ref48>;
442 clock-names = "xtal";
443 clock-output-names = "si5341";
Michal Simekc13291f2019-08-06 12:07:10 +0200444
Michal Simek958c0e92020-11-26 14:25:02 +0100445 si5341_2: out@2 {
446 /* refclk2 for PS-GT, used for USB3 */
447 reg = <2>;
Michal Simek94d1ae12021-03-11 13:34:02 +0100448 always-on;
Michal Simek958c0e92020-11-26 14:25:02 +0100449 };
450 si5341_3: out@3 {
451 /* refclk3 for PS-GT, used for SATA */
452 reg = <3>;
Michal Simek94d1ae12021-03-11 13:34:02 +0100453 always-on;
Michal Simek958c0e92020-11-26 14:25:02 +0100454 };
455 si5341_5: out@5 {
456 /* refclk5 PL CLK100 */
457 reg = <5>;
Michal Simek94d1ae12021-03-11 13:34:02 +0100458 always-on;
Michal Simek958c0e92020-11-26 14:25:02 +0100459 };
460 si5341_6: out@6 {
461 /* refclk6 PL CLK125 */
462 reg = <6>;
Michal Simek94d1ae12021-03-11 13:34:02 +0100463 always-on;
Michal Simek958c0e92020-11-26 14:25:02 +0100464 };
465 si5341_9: out@9 {
466 /* refclk9 used for PS_REF_CLK 33.3 MHz */
467 reg = <9>;
Michal Simek94d1ae12021-03-11 13:34:02 +0100468 always-on;
Michal Simek958c0e92020-11-26 14:25:02 +0100469 };
470 };
Michal Simekc13291f2019-08-06 12:07:10 +0200471 };
472 i2c_si570_user_c0: i2c@2 {
473 #address-cells = <1>;
474 #size-cells = <0>;
475 reg = <2>;
476 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
477 #clock-cells = <0>;
478 compatible = "silabs,si570";
479 reg = <0x5d>;
480 temperature-stability = <50>;
481 factory-fout = <300000000>;
482 clock-frequency = <300000000>;
483 clock-output-names = "si570_user_c0";
484 };
485 };
486 i2c_si570_mgt: i2c@3 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 reg = <3>;
490 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
491 #clock-cells = <0>;
492 compatible = "silabs,si570";
493 reg = <0x5d>;
494 temperature-stability = <50>;
495 factory-fout = <156250000>;
496 clock-frequency = <148500000>;
497 clock-output-names = "si570_mgt";
498 };
499 };
500 i2c_8a34001: i2c@4 {
501 #address-cells = <1>;
502 #size-cells = <0>;
503 reg = <4>;
Michal Simek1c4e7da2021-01-22 14:42:29 +0100504 idt_8a34001: phc@5b {
505 compatible = "idt,8a34001"; /* u409B */
506 reg = <0x5b>;
507 };
Michal Simekc13291f2019-08-06 12:07:10 +0200508 };
509 i2c_clk104: i2c@5 {
510 #address-cells = <1>;
511 #size-cells = <0>;
512 reg = <5>;
513 /* CLK104_SDA */
514 };
515 i2c@6 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <6>;
519 /* RFMCP connector */
520 };
521 /* 7 NC */
522 };
523
524 i2c-mux@75 {
525 compatible = "nxp,pca9548"; /* u22 */
526 #address-cells = <1>;
527 #size-cells = <0>;
528 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600529 i2c-mux-idle-disconnect;
Michal Simekc13291f2019-08-06 12:07:10 +0200530 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
531 i2c@0 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 reg = <0>;
535 /* FMCP_HSPC_IIC */
536 };
537 i2c_si570_user_c1: i2c@1 {
538 #address-cells = <1>;
539 #size-cells = <0>;
540 reg = <1>;
541 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
542 #clock-cells = <0>;
543 compatible = "silabs,si570";
544 reg = <0x5d>;
545 temperature-stability = <50>;
546 factory-fout = <300000000>;
547 clock-frequency = <300000000>;
548 clock-output-names = "si570_user_c1";
549 };
550 };
551 i2c@2 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 reg = <2>;
555 /* SYSMON */
556 };
557 i2c@3 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 reg = <3>;
561 /* DDR4 SODIMM */
562 };
563 i2c@4 {
564 #address-cells = <1>;
565 #size-cells = <0>;
566 reg = <4>;
567 /* SFP3 */
568 };
569 i2c@5 {
570 #address-cells = <1>;
571 #size-cells = <0>;
572 reg = <5>;
573 /* SFP2 */
574 };
575 i2c@6 {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 reg = <6>;
579 /* SFP1 */
580 };
581 i2c@7 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 reg = <7>;
585 /* SFP0 */
586 };
587 };
588 /* MSP430 */
589};
590
Michal Simekf7b922a2021-05-10 13:14:02 +0200591&pinctrl0 {
592 status = "okay";
593 pinctrl_i2c0_default: i2c0-default {
594 mux {
595 groups = "i2c0_3_grp";
596 function = "i2c0";
597 };
598
599 conf {
600 groups = "i2c0_3_grp";
601 bias-pull-up;
602 slew-rate = <SLEW_RATE_SLOW>;
603 power-source = <IO_STANDARD_LVCMOS18>;
604 };
605 };
606
607 pinctrl_i2c0_gpio: i2c0-gpio {
608 mux {
609 groups = "gpio0_14_grp", "gpio0_15_grp";
610 function = "gpio0";
611 };
612
613 conf {
614 groups = "gpio0_14_grp", "gpio0_15_grp";
615 slew-rate = <SLEW_RATE_SLOW>;
616 power-source = <IO_STANDARD_LVCMOS18>;
617 };
618 };
619
620 pinctrl_i2c1_default: i2c1-default {
621 mux {
622 groups = "i2c1_4_grp";
623 function = "i2c1";
624 };
625
626 conf {
627 groups = "i2c1_4_grp";
628 bias-pull-up;
629 slew-rate = <SLEW_RATE_SLOW>;
630 power-source = <IO_STANDARD_LVCMOS18>;
631 };
632 };
633
634 pinctrl_i2c1_gpio: i2c1-gpio {
635 mux {
636 groups = "gpio0_16_grp", "gpio0_17_grp";
637 function = "gpio0";
638 };
639
640 conf {
641 groups = "gpio0_16_grp", "gpio0_17_grp";
642 slew-rate = <SLEW_RATE_SLOW>;
643 power-source = <IO_STANDARD_LVCMOS18>;
644 };
645 };
646};
647
Michal Simekc13291f2019-08-06 12:07:10 +0200648&qspi {
649 status = "okay";
650 is-dual = <1>;
651 flash@0 {
652 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
653 #address-cells = <1>;
654 #size-cells = <1>;
655 reg = <0x0>;
656 spi-tx-bus-width = <1>;
657 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
658 spi-max-frequency = <108000000>; /* Based on DC1 spec */
659 };
660};
661
662&rtc {
663 status = "okay";
664};
665
666&sata {
667 status = "okay";
668 /* SATA OOB timing settings */
669 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
670 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
671 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
672 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
673 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
674 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
675 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
676 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
Michal Simekfe8cb0c2021-05-10 14:55:34 +0200677 phy-names = "sata-phy";
Michal Simek958c0e92020-11-26 14:25:02 +0100678 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
Michal Simekc13291f2019-08-06 12:07:10 +0200679};
680
681/* SD1 with level shifter */
682&sdhci1 {
683 status = "okay";
684 disable-wp;
Manish Naranie2ba0932020-02-13 23:37:30 -0700685 /*
686 * This property should be removed for supporting UHS mode
687 */
688 no-1-8-v;
Michal Simek3b662642020-07-22 17:42:43 +0200689 xlnx,mio-bank = <1>;
Michal Simekc13291f2019-08-06 12:07:10 +0200690};
691
Michal Simekc13291f2019-08-06 12:07:10 +0200692&uart0 {
693 status = "okay";
694};
695
696/* ULPI SMSC USB3320 */
697&usb0 {
698 status = "okay";
699};
700
701&dwc3_0 {
702 status = "okay";
703 dr_mode = "host";
704 snps,usb3_lpm_capable;
Michal Simekfe8cb0c2021-05-10 14:55:34 +0200705 phy-names = "usb3-phy";
706 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
Michal Simekeb4b55c2021-05-31 17:51:58 +0200707 maximum-speed = "super-speed";
Michal Simekc13291f2019-08-06 12:07:10 +0200708};