wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 Embedded Edge, LLC |
| 3 | * Dan Malek <dan@embeddededge.com> |
| 4 | * Copied from ADS85xx. |
| 5 | * Updates for Silicon Tx GP3 8560 board. |
| 6 | * |
| 7 | * (C) Copyright 2002,2003 Motorola,Inc. |
| 8 | * Xianghua Xiao <X.Xiao@motorola.com> |
| 9 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | /* mpc8560ads board configuration file */ |
| 14 | /* please refer to doc/README.mpc85xx for more info */ |
| 15 | /* make sure you change the MAC address and other network params first, |
| 16 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file |
| 17 | */ |
| 18 | |
| 19 | #ifndef __CONFIG_H |
| 20 | #define __CONFIG_H |
| 21 | |
| 22 | /* High Level Configuration Options */ |
| 23 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 24 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 25 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
Jon Loeliger | f5ad378 | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 26 | #define CONFIG_CPM2 1 /* has CPM2 */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 27 | #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ |
Kumar Gala | 75639e0 | 2008-06-11 00:44:10 -0500 | [diff] [blame] | 28 | #define CONFIG_MPC8560 1 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 29 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 30 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
| 31 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 32 | #undef CONFIG_PCI /* pci ethernet support */ |
| 33 | #define CONFIG_TSEC_ENET /* tsec ethernet support*/ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 34 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
| 35 | #define CONFIG_ENV_OVERWRITE |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 36 | |
Kumar Gala | a3b76c5 | 2008-01-16 09:11:53 -0600 | [diff] [blame] | 37 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 38 | |
| 39 | /* sysclk for MPC85xx |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 40 | */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 41 | |
| 42 | #define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ |
| 43 | |
| 44 | /* Blinkin' LEDs for Robert :-) |
| 45 | */ |
| 46 | #define CONFIG_SHOW_ACTIVITY 1 |
| 47 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 48 | /* |
| 49 | * These can be toggled for performance analysis, otherwise use default. |
| 50 | */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 51 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 52 | #define CONFIG_BTB /* toggle branch predition */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 53 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 54 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
Peter Tyser | d3d9a50 | 2009-09-16 22:03:08 -0500 | [diff] [blame] | 55 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 56 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 58 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 59 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 60 | |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 61 | |
| 62 | /* Localbus SDRAM is an option, not all boards have it. |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 63 | * This address, however, is used to configure a 256M local bus |
| 64 | * window that includes the Config latch below. |
| 65 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| 67 | #define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 68 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
| 70 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 71 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ |
| 73 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 74 | #define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */ |
| 75 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 76 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ |
| 77 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 78 | |
| 79 | /* The configuration latch is Chip Select 1. |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 80 | * It's an 8-bit latch in the lower 8 bits of the word. |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 81 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 82 | #define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */ |
| 83 | #define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ |
| 84 | #define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 85 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 86 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 87 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 89 | #define CONFIG_SYS_RAMBOOT |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 90 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 91 | #undef CONFIG_SYS_RAMBOOT |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 92 | #endif |
| 93 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | #ifdef CONFIG_SYS_RAMBOOT |
| 95 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 96 | #endif |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 97 | #define CONFIG_SYS_CCSRBAR 0xfdf00000 |
| 98 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 99 | |
Kumar Gala | 5b4ae73 | 2008-08-27 01:03:42 -0500 | [diff] [blame] | 100 | /* DDR Setup */ |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 101 | #define CONFIG_SYS_FSL_DDR1 |
Kumar Gala | 5b4ae73 | 2008-08-27 01:03:42 -0500 | [diff] [blame] | 102 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 103 | #define CONFIG_DDR_SPD |
| 104 | #undef CONFIG_FSL_DDR_INTERACTIVE |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 105 | |
Kumar Gala | 5b4ae73 | 2008-08-27 01:03:42 -0500 | [diff] [blame] | 106 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
Becky Bruce | 4212f23 | 2010-12-17 17:17:58 -0600 | [diff] [blame] | 107 | #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ |
Kumar Gala | 5b4ae73 | 2008-08-27 01:03:42 -0500 | [diff] [blame] | 108 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 109 | |
Kumar Gala | 5b4ae73 | 2008-08-27 01:03:42 -0500 | [diff] [blame] | 110 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 111 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 113 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 114 | |
Kumar Gala | 5b4ae73 | 2008-08-27 01:03:42 -0500 | [diff] [blame] | 115 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 116 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 117 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 118 | |
| 119 | /* I2C addresses of SPD EEPROMs */ |
| 120 | #define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 121 | |
| 122 | #undef CONFIG_CLOCKS_IN_MHZ |
| 123 | |
| 124 | /* local bus definitions */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 125 | #define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ |
| 126 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
| 127 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ |
| 128 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 129 | #define CONFIG_SYS_LBC_LSRT 0x20000000 |
| 130 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 |
| 131 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 |
| 132 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 |
| 133 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 |
| 134 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 |
| 135 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 136 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 137 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 138 | #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 139 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 140 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 141 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 143 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 144 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 145 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 146 | |
| 147 | /* Serial Port */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 148 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
| 149 | #undef CONFIG_CONS_NONE /* define if console on something else */ |
| 150 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 151 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 152 | #define CONFIG_BAUDRATE 38400 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 153 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 155 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 156 | |
| 157 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_HUSH_PARSER |
| 159 | #ifdef CONFIG_SYS_HUSH_PARSER |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 160 | #endif |
| 161 | |
Jon Loeliger | 43d818f | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 162 | /* |
| 163 | * I2C |
| 164 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_I2C |
| 166 | #define CONFIG_SYS_I2C_FSL |
| 167 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 168 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 169 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 170 | |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 171 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 173 | #else |
| 174 | /* I did the 'if 0' so we could keep the syntax above if ever needed. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #undef CONFIG_SYS_I2C_NOPROBES |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 176 | #endif |
| 177 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 178 | /* RapdIO Map configuration, mapped 1:1. |
| 179 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 |
| 181 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE |
| 182 | #define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 183 | |
| 184 | /* Standard 8560 PCI addressing, mapped 1:1. |
| 185 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 187 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
| 188 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 189 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 |
| 190 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE |
| 191 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 192 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 193 | #if defined(CONFIG_PCI) /* PCI Ethernet card */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 194 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 195 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 196 | |
| 197 | #undef CONFIG_EEPRO100 |
| 198 | #undef CONFIG_TULIP |
| 199 | |
| 200 | #if !defined(CONFIG_PCI_PNP) |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 201 | #define PCI_ENET0_IOADDR 0xe0000000 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 202 | #define PCI_ENET0_MEMADDR 0xe0000000 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 203 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 204 | #endif |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 205 | |
| 206 | #undef CONFIG_PCI_SCAN_SHOW |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 208 | |
| 209 | #endif /* CONFIG_PCI */ |
| 210 | |
| 211 | #if defined(CONFIG_TSEC_ENET) |
| 212 | |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 213 | #define CONFIG_MII 1 /* MII PHY management */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 214 | |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 215 | #define CONFIG_TSEC1 1 |
| 216 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 217 | #define CONFIG_TSEC2 1 |
| 218 | #define CONFIG_TSEC2_NAME "TSEC1" |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 219 | |
| 220 | #define TSEC1_PHY_ADDR 2 |
| 221 | #define TSEC2_PHY_ADDR 4 |
| 222 | #define TSEC1_PHYIDX 0 |
| 223 | #define TSEC2_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 224 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 225 | #define TSEC2_FLAGS TSEC_GIGABIT |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 226 | #define CONFIG_ETHPRIME "TSEC0" |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 227 | |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 228 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 229 | |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 230 | #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ |
| 231 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
| 232 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 233 | |
| 234 | #if (CONFIG_ETHER_INDEX == 2) |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 235 | /* |
| 236 | * - Rx-CLK is CLK13 |
| 237 | * - Tx-CLK is CLK14 |
| 238 | * - Select bus for bd/buffers |
| 239 | * - Full duplex |
| 240 | */ |
Mike Frysinger | 109de97 | 2011-10-17 05:38:58 +0000 | [diff] [blame] | 241 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
| 242 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 243 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 244 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 246 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_FCC_PSMR 0 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 248 | #endif |
| 249 | #define FETH2_RST 0x01 |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 250 | #elif (CONFIG_ETHER_INDEX == 3) |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 251 | /* need more definitions here for FE3 */ |
| 252 | #define FETH3_RST 0x80 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 253 | #endif /* CONFIG_ETHER_INDEX */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 254 | |
| 255 | /* MDIO is done through the TSEC0 control. |
| 256 | */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 257 | #define CONFIG_MII /* MII PHY management */ |
| 258 | #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 259 | |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 260 | #endif |
| 261 | |
| 262 | /* Environment */ |
| 263 | /* We use the top boot sector flash, so we have some 16K sectors for env |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 264 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 265 | #ifndef CONFIG_SYS_RAMBOOT |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 266 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 268 | #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ |
| 269 | #define CONFIG_ENV_SIZE 0x2000 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 270 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 271 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
Jean-Christophe PLAGNIOL-VILLARD | 68a8756 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 272 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 273 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 274 | #define CONFIG_ENV_SIZE 0x2000 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 275 | #endif |
| 276 | |
| 277 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 278 | #define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 279 | #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
| 280 | |
| 281 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 282 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 283 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 284 | /* |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 285 | * BOOTP options |
| 286 | */ |
| 287 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 288 | #define CONFIG_BOOTP_BOOTPATH |
| 289 | #define CONFIG_BOOTP_GATEWAY |
| 290 | #define CONFIG_BOOTP_HOSTNAME |
| 291 | |
| 292 | |
| 293 | /* |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 294 | * Command line configuration. |
| 295 | */ |
| 296 | #include <config_cmd_default.h> |
| 297 | |
| 298 | #define CONFIG_CMD_PING |
| 299 | #define CONFIG_CMD_I2C |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 300 | #define CONFIG_CMD_REGINFO |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 301 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 302 | #if defined(CONFIG_SYS_RAMBOOT) |
Mike Frysinger | 78dcaf4 | 2009-01-28 19:08:14 -0500 | [diff] [blame] | 303 | #undef CONFIG_CMD_SAVEENV |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 304 | #undef CONFIG_CMD_LOADS |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 305 | #else |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 306 | #define CONFIG_CMD_ELF |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 307 | #endif |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 308 | |
| 309 | #if defined(CONFIG_PCI) |
| 310 | #define CONFIG_CMD_PCI |
| 311 | #endif |
| 312 | |
| 313 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
| 314 | #define CONFIG_CMD_MII |
| 315 | #endif |
| 316 | |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 317 | |
| 318 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 319 | |
| 320 | /* |
| 321 | * Miscellaneous configurable options |
| 322 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 323 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 324 | #define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */ |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 325 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 326 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 327 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 328 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 329 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 330 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 331 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 332 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 333 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 334 | |
| 335 | /* |
| 336 | * For booting Linux, the board info and command line data |
| 337 | * have to be in the first 8 MB of memory, since this is |
| 338 | * the maximum mapped by the Linux kernel during initialization. |
| 339 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 340 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 341 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 342 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 343 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 344 | #endif |
| 345 | |
| 346 | /*Note: change below for your network setting!!! */ |
| 347 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 348 | #define CONFIG_HAS_ETH0 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 349 | #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 350 | #define CONFIG_HAS_ETH1 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 351 | #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 352 | #define CONFIG_HAS_ETH2 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 353 | #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 354 | #endif |
| 355 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 356 | #define CONFIG_SERVERIP 192.168.85.1 |
| 357 | #define CONFIG_IPADDR 192.168.85.60 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 358 | #define CONFIG_GATEWAYIP 192.168.85.1 |
| 359 | #define CONFIG_NETMASK 255.255.255.0 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 360 | #define CONFIG_HOSTNAME STX_GP3 |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 361 | #define CONFIG_ROOTPATH "/gppproot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 362 | #define CONFIG_BOOTFILE "uImage" |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 363 | #define CONFIG_LOADADDR 0x1000000 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 364 | |
| 365 | #endif /* __CONFIG_H */ |