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wdenk78924a72004-04-18 21:45:42 +00001/*
2 * (C) Copyright 2003 Embedded Edge, LLC
3 * Dan Malek <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560 board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk78924a72004-04-18 21:45:42 +000011 */
12
13/* mpc8560ads board configuration file */
14/* please refer to doc/README.mpc85xx for more info */
15/* make sure you change the MAC address and other network params first,
16 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
17 */
18
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/* High Level Configuration Options */
23#define CONFIG_BOOKE 1 /* BOOKE */
24#define CONFIG_E500 1 /* BOOKE e500 family */
25#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050026#define CONFIG_CPM2 1 /* has CPM2 */
wdenk78924a72004-04-18 21:45:42 +000027#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
Kumar Gala75639e02008-06-11 00:44:10 -050028#define CONFIG_MPC8560 1
wdenk78924a72004-04-18 21:45:42 +000029
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020030#define CONFIG_SYS_TEXT_BASE 0xfff80000
31
Wolfgang Denka1be4762008-05-20 16:00:29 +020032#undef CONFIG_PCI /* pci ethernet support */
33#define CONFIG_TSEC_ENET /* tsec ethernet support*/
wdenk78924a72004-04-18 21:45:42 +000034#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
35#define CONFIG_ENV_OVERWRITE
wdenk78924a72004-04-18 21:45:42 +000036
Kumar Galaa3b76c52008-01-16 09:11:53 -060037#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk492b9e72004-08-01 23:02:45 +000038
39/* sysclk for MPC85xx
wdenk78924a72004-04-18 21:45:42 +000040 */
wdenk78924a72004-04-18 21:45:42 +000041
42#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
43
44/* Blinkin' LEDs for Robert :-)
45*/
46#define CONFIG_SHOW_ACTIVITY 1
47
wdenk492b9e72004-08-01 23:02:45 +000048/*
49 * These can be toggled for performance analysis, otherwise use default.
50 */
wdenk78924a72004-04-18 21:45:42 +000051#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk492b9e72004-08-01 23:02:45 +000052#define CONFIG_BTB /* toggle branch predition */
wdenk78924a72004-04-18 21:45:42 +000053
wdenk492b9e72004-08-01 23:02:45 +000054#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Peter Tyserd3d9a502009-09-16 22:03:08 -050055#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk78924a72004-04-18 21:45:42 +000056
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
58#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
59#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk78924a72004-04-18 21:45:42 +000060
wdenk78924a72004-04-18 21:45:42 +000061
62/* Localbus SDRAM is an option, not all boards have it.
wdenk492b9e72004-08-01 23:02:45 +000063 * This address, however, is used to configure a 256M local bus
64 * window that includes the Config latch below.
65 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
67#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
wdenk78924a72004-04-18 21:45:42 +000068
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
70#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk78924a72004-04-18 21:45:42 +000071
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
73#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
74#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */
75#undef CONFIG_SYS_FLASH_CHECKSUM
76#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
77#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk78924a72004-04-18 21:45:42 +000078
79/* The configuration latch is Chip Select 1.
wdenk492b9e72004-08-01 23:02:45 +000080 * It's an 8-bit latch in the lower 8 bits of the word.
wdenk78924a72004-04-18 21:45:42 +000081 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */
83#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
84#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
wdenk78924a72004-04-18 21:45:42 +000085
Wolfgang Denk0708bc62010-10-07 21:51:12 +020086#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk78924a72004-04-18 21:45:42 +000087
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
89#define CONFIG_SYS_RAMBOOT
wdenk78924a72004-04-18 21:45:42 +000090#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#undef CONFIG_SYS_RAMBOOT
wdenk78924a72004-04-18 21:45:42 +000092#endif
93
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#ifdef CONFIG_SYS_RAMBOOT
95#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
wdenk78924a72004-04-18 21:45:42 +000096#endif
Timur Tabid8f341c2011-08-04 18:03:41 -050097#define CONFIG_SYS_CCSRBAR 0xfdf00000
98#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk78924a72004-04-18 21:45:42 +000099
Kumar Gala5b4ae732008-08-27 01:03:42 -0500100/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -0700101#define CONFIG_SYS_FSL_DDR1
Kumar Gala5b4ae732008-08-27 01:03:42 -0500102#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
103#define CONFIG_DDR_SPD
104#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk78924a72004-04-18 21:45:42 +0000105
Kumar Gala5b4ae732008-08-27 01:03:42 -0500106#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Becky Bruce4212f232010-12-17 17:17:58 -0600107#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
Kumar Gala5b4ae732008-08-27 01:03:42 -0500108#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk78924a72004-04-18 21:45:42 +0000109
Kumar Gala5b4ae732008-08-27 01:03:42 -0500110#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
113#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk492b9e72004-08-01 23:02:45 +0000114
Kumar Gala5b4ae732008-08-27 01:03:42 -0500115#define CONFIG_NUM_DDR_CONTROLLERS 1
116#define CONFIG_DIMM_SLOTS_PER_CTLR 1
117#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
118
119/* I2C addresses of SPD EEPROMs */
120#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
wdenk78924a72004-04-18 21:45:42 +0000121
122#undef CONFIG_CLOCKS_IN_MHZ
123
124/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
126#define CONFIG_SYS_OR2_PRELIM 0xfc006901
127#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
128#define CONFIG_SYS_LBC_LBCR 0x00000000
129#define CONFIG_SYS_LBC_LSRT 0x20000000
130#define CONFIG_SYS_LBC_MRTPR 0x20000000
131#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
132#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
133#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
134#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
135#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenk78924a72004-04-18 21:45:42 +0000136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_INIT_RAM_LOCK 1
138#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200139#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk78924a72004-04-18 21:45:42 +0000140
Wolfgang Denk0191e472010-10-26 14:34:52 +0200141#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk78924a72004-04-18 21:45:42 +0000143
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
145#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk78924a72004-04-18 21:45:42 +0000146
147/* Serial Port */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200148#define CONFIG_CONS_ON_SCC /* define if console on SCC */
149#undef CONFIG_CONS_NONE /* define if console on something else */
150#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
wdenk78924a72004-04-18 21:45:42 +0000151
Wolfgang Denka1be4762008-05-20 16:00:29 +0200152#define CONFIG_BAUDRATE 38400
wdenk78924a72004-04-18 21:45:42 +0000153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk78924a72004-04-18 21:45:42 +0000155 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
156
157/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_HUSH_PARSER
159#ifdef CONFIG_SYS_HUSH_PARSER
wdenk78924a72004-04-18 21:45:42 +0000160#endif
161
Jon Loeliger43d818f2006-10-20 15:50:15 -0500162/*
163 * I2C
164 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200165#define CONFIG_SYS_I2C
166#define CONFIG_SYS_I2C_FSL
167#define CONFIG_SYS_FSL_I2C_SPEED 400000
168#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
169#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
170
wdenk78924a72004-04-18 21:45:42 +0000171#if 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
wdenk78924a72004-04-18 21:45:42 +0000173#else
174/* I did the 'if 0' so we could keep the syntax above if ever needed. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#undef CONFIG_SYS_I2C_NOPROBES
wdenk78924a72004-04-18 21:45:42 +0000176#endif
177
wdenk492b9e72004-08-01 23:02:45 +0000178/* RapdIO Map configuration, mapped 1:1.
179*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
181#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
182#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
wdenk492b9e72004-08-01 23:02:45 +0000183
184/* Standard 8560 PCI addressing, mapped 1:1.
185*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
187#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
188#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
189#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
190#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
191#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
wdenk78924a72004-04-18 21:45:42 +0000192
Wolfgang Denka1be4762008-05-20 16:00:29 +0200193#if defined(CONFIG_PCI) /* PCI Ethernet card */
wdenk492b9e72004-08-01 23:02:45 +0000194
Wolfgang Denka1be4762008-05-20 16:00:29 +0200195#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk492b9e72004-08-01 23:02:45 +0000196
197#undef CONFIG_EEPRO100
198#undef CONFIG_TULIP
199
200#if !defined(CONFIG_PCI_PNP)
Wolfgang Denka1be4762008-05-20 16:00:29 +0200201 #define PCI_ENET0_IOADDR 0xe0000000
wdenk78924a72004-04-18 21:45:42 +0000202 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denka1be4762008-05-20 16:00:29 +0200203 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk78924a72004-04-18 21:45:42 +0000204#endif
wdenk492b9e72004-08-01 23:02:45 +0000205
206#undef CONFIG_PCI_SCAN_SHOW
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk492b9e72004-08-01 23:02:45 +0000208
209#endif /* CONFIG_PCI */
210
211#if defined(CONFIG_TSEC_ENET)
212
wdenk78924a72004-04-18 21:45:42 +0000213#define CONFIG_MII 1 /* MII PHY management */
wdenk492b9e72004-08-01 23:02:45 +0000214
Kim Phillips177e58f2007-05-16 16:52:19 -0500215#define CONFIG_TSEC1 1
216#define CONFIG_TSEC1_NAME "TSEC0"
217#define CONFIG_TSEC2 1
218#define CONFIG_TSEC2_NAME "TSEC1"
wdenk492b9e72004-08-01 23:02:45 +0000219
220#define TSEC1_PHY_ADDR 2
221#define TSEC2_PHY_ADDR 4
222#define TSEC1_PHYIDX 0
223#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500224#define TSEC1_FLAGS TSEC_GIGABIT
225#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500226#define CONFIG_ETHPRIME "TSEC0"
wdenk492b9e72004-08-01 23:02:45 +0000227
wdenk78924a72004-04-18 21:45:42 +0000228#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
wdenk492b9e72004-08-01 23:02:45 +0000229
wdenk78924a72004-04-18 21:45:42 +0000230#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
231#undef CONFIG_ETHER_NONE /* define if ether on something else */
232#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk492b9e72004-08-01 23:02:45 +0000233
234#if (CONFIG_ETHER_INDEX == 2)
wdenk78924a72004-04-18 21:45:42 +0000235 /*
236 * - Rx-CLK is CLK13
237 * - Tx-CLK is CLK14
238 * - Select bus for bd/buffers
239 * - Full duplex
240 */
Mike Frysinger109de972011-10-17 05:38:58 +0000241 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
242 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
wdenk78924a72004-04-18 21:45:42 +0000244#if 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk78924a72004-04-18 21:45:42 +0000246#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247 #define CONFIG_SYS_FCC_PSMR 0
wdenk78924a72004-04-18 21:45:42 +0000248#endif
249 #define FETH2_RST 0x01
wdenk492b9e72004-08-01 23:02:45 +0000250#elif (CONFIG_ETHER_INDEX == 3)
wdenk78924a72004-04-18 21:45:42 +0000251 /* need more definitions here for FE3 */
252 #define FETH3_RST 0x80
Wolfgang Denka1be4762008-05-20 16:00:29 +0200253#endif /* CONFIG_ETHER_INDEX */
wdenk492b9e72004-08-01 23:02:45 +0000254
255/* MDIO is done through the TSEC0 control.
256*/
wdenk78924a72004-04-18 21:45:42 +0000257#define CONFIG_MII /* MII PHY management */
258#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
wdenk78924a72004-04-18 21:45:42 +0000259
wdenk78924a72004-04-18 21:45:42 +0000260#endif
261
262/* Environment */
263/* We use the top boot sector flash, so we have some 16K sectors for env
wdenk78924a72004-04-18 21:45:42 +0000264 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200266 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200268 #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
269 #define CONFIG_ENV_SIZE 0x2000
wdenk78924a72004-04-18 21:45:42 +0000270#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200272 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200274 #define CONFIG_ENV_SIZE 0x2000
wdenk78924a72004-04-18 21:45:42 +0000275#endif
276
277#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
wdenk492b9e72004-08-01 23:02:45 +0000278#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
wdenk78924a72004-04-18 21:45:42 +0000279#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
280
281#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk78924a72004-04-18 21:45:42 +0000283
Jon Loeligere63319f2007-06-13 13:22:08 -0500284/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500285 * BOOTP options
286 */
287#define CONFIG_BOOTP_BOOTFILESIZE
288#define CONFIG_BOOTP_BOOTPATH
289#define CONFIG_BOOTP_GATEWAY
290#define CONFIG_BOOTP_HOSTNAME
291
292
293/*
Jon Loeligere63319f2007-06-13 13:22:08 -0500294 * Command line configuration.
295 */
296#include <config_cmd_default.h>
297
298#define CONFIG_CMD_PING
299#define CONFIG_CMD_I2C
Becky Bruceee888da2010-06-17 11:37:25 -0500300#define CONFIG_CMD_REGINFO
Jon Loeligere63319f2007-06-13 13:22:08 -0500301
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200302#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysinger78dcaf42009-01-28 19:08:14 -0500303 #undef CONFIG_CMD_SAVEENV
Jon Loeligere63319f2007-06-13 13:22:08 -0500304 #undef CONFIG_CMD_LOADS
wdenk78924a72004-04-18 21:45:42 +0000305#else
Jon Loeligere63319f2007-06-13 13:22:08 -0500306 #define CONFIG_CMD_ELF
wdenk78924a72004-04-18 21:45:42 +0000307#endif
Jon Loeligere63319f2007-06-13 13:22:08 -0500308
309#if defined(CONFIG_PCI)
310 #define CONFIG_CMD_PCI
311#endif
312
313#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
314 #define CONFIG_CMD_MII
315#endif
316
wdenk78924a72004-04-18 21:45:42 +0000317
318#undef CONFIG_WATCHDOG /* watchdog disabled */
319
320/*
321 * Miscellaneous configurable options
322 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200323#define CONFIG_SYS_LONGHELP /* undef to save memory */
324#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */
Jon Loeligere63319f2007-06-13 13:22:08 -0500325#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200326#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk78924a72004-04-18 21:45:42 +0000327#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200328#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk78924a72004-04-18 21:45:42 +0000329#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
331#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
332#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
333#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk78924a72004-04-18 21:45:42 +0000334
335/*
336 * For booting Linux, the board info and command line data
337 * have to be in the first 8 MB of memory, since this is
338 * the maximum mapped by the Linux kernel during initialization.
339 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200340#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk78924a72004-04-18 21:45:42 +0000341
Jon Loeligere63319f2007-06-13 13:22:08 -0500342#if defined(CONFIG_CMD_KGDB)
wdenk78924a72004-04-18 21:45:42 +0000343#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk78924a72004-04-18 21:45:42 +0000344#endif
345
346/*Note: change below for your network setting!!! */
347#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming458c3892007-08-16 16:35:02 -0500348#define CONFIG_HAS_ETH0
Wolfgang Denka1be4762008-05-20 16:00:29 +0200349#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
wdenk54070ab2004-12-31 09:32:47 +0000350#define CONFIG_HAS_ETH1
Wolfgang Denka1be4762008-05-20 16:00:29 +0200351#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
wdenk54070ab2004-12-31 09:32:47 +0000352#define CONFIG_HAS_ETH2
Wolfgang Denka1be4762008-05-20 16:00:29 +0200353#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
wdenk78924a72004-04-18 21:45:42 +0000354#endif
355
Wolfgang Denka1be4762008-05-20 16:00:29 +0200356#define CONFIG_SERVERIP 192.168.85.1
357#define CONFIG_IPADDR 192.168.85.60
wdenk78924a72004-04-18 21:45:42 +0000358#define CONFIG_GATEWAYIP 192.168.85.1
359#define CONFIG_NETMASK 255.255.255.0
Wolfgang Denka1be4762008-05-20 16:00:29 +0200360#define CONFIG_HOSTNAME STX_GP3
Joe Hershberger257ff782011-10-13 13:03:47 +0000361#define CONFIG_ROOTPATH "/gppproot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000362#define CONFIG_BOOTFILE "uImage"
wdenk492b9e72004-08-01 23:02:45 +0000363#define CONFIG_LOADADDR 0x1000000
wdenk78924a72004-04-18 21:45:42 +0000364
365#endif /* __CONFIG_H */