blob: a13778830a3b9e01445fc79a3e0832fb4d8dd2ee [file] [log] [blame]
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09001/*
2 * Configuation settings for the Renesas SH7763RDP board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09008 */
9
10#ifndef __SH7763RDP_H
11#define __SH7763RDP_H
12
13#define CONFIG_SH 1
14#define CONFIG_SH4 1
15#define CONFIG_CPU_SH7763 1
16#define CONFIG_SH7763RDP 1
17#define __LITTLE_ENDIAN 1
18
19/*
20 * Command line configuration.
21 */
22#define CONFIG_CMD_SDRAM
23#define CONFIG_CMD_FLASH
24#define CONFIG_CMD_MEMORY
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090025#define CONFIG_CMD_NET
Yoshihiro Shimodac578baa2011-10-31 10:44:18 +090026#define CONFIG_CMD_MII
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090027#define CONFIG_CMD_PING
Mike Frysinger78dcaf42009-01-28 19:08:14 -050028#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090029#define CONFIG_CMD_NFS
30#define CONFIG_CMD_JFFS2
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090031
32#define CONFIG_BOOTDELAY -1
33#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
34#define CONFIG_ENV_OVERWRITE 1
35
36#define CONFIG_VERSION_VARIABLE
37#undef CONFIG_SHOW_BOOT_PROGRESS
38
39/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020040#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090041#define CONFIG_BAUDRATE 115200
42#define CONFIG_CONS_SCIF2 1
43
Nobuhiro Iwamatsu69633662011-01-17 20:53:29 +090044#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
47#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
48#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
49#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090050 passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090052 settings for this board */
53
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090054/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
56#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
57#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
58#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090059
60/* Flash(NOR) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_FLASH_BASE (0xA0000000)
62#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
63#define CONFIG_SYS_MAX_FLASH_BANKS (1)
64#define CONFIG_SYS_MAX_FLASH_SECT (520)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090065
66/* U-boot setting */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
68#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
69#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090070/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090073
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020075#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#undef CONFIG_SYS_FLASH_QUIET_TEST
77#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090078/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090080/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090082/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090084/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090086/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#undef CONFIG_SYS_FLASH_PROTECTION
88#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020089#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020090#define CONFIG_ENV_SECT_SIZE (128 * 1024)
91#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
93/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
94#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020095#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090097
98/* Clock */
99#define CONFIG_SYS_CLK_FREQ 66666666
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +0900100#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
101#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200102#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900103
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +0900104/* Ether */
105#define CONFIG_SH_ETHER 1
106#define CONFIG_SH_ETHER_USE_PORT (1)
107#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
Yoshihiro Shimodac578baa2011-10-31 10:44:18 +0900108#define CONFIG_PHYLIB
109#define CONFIG_BITBANGMII
110#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsu32f900e2012-05-16 10:23:21 +0900111#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +0900112
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900113#endif /* __SH7763RDP_H */