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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the R&S Protocol Board board.
10 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +000012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
22#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
23#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050024#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenke2211742002-11-02 23:30:20 +000025
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xff000000
Wolfgang Denk341e5e72010-11-28 21:18:58 +010027#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds"
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020028
wdenkda55c6e2004-01-20 23:12:12 +000029#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
30
wdenke2211742002-11-02 23:30:20 +000031/*
32 * select serial console configuration
33 *
34 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
35 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
36 * for SCC).
37 *
38 * if CONFIG_CONS_NONE is defined, then the serial console routines must
39 * defined elsewhere.
40 */
41#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
42#define CONFIG_CONS_ON_SCC /* define if console on SCC */
Wolfgang Denka1be4762008-05-20 16:00:29 +020043#undef CONFIG_CONS_NONE /* define if console on neither */
wdenke2211742002-11-02 23:30:20 +000044#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
45
46/*
47 * select ethernet configuration
48 *
49 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
50 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
51 * for FCC)
52 *
53 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger2517d972007-07-09 17:15:49 -050054 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000055 */
56#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
57#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
58#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
59#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
60
61#if (CONFIG_ETHER_INDEX == 2)
62
63/*
64 * - Rx-CLK is CLK13
65 * - Tx-CLK is CLK14
66 * - Select bus for bd/buffers (see 28-13)
67 * - Enable Full Duplex in FSMR
68 */
Mike Frysinger109de972011-10-17 05:38:58 +000069# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
70# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
72# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenke2211742002-11-02 23:30:20 +000073
74#endif /* CONFIG_ETHER_INDEX */
75
76
77/* allow to overwrite serial and ethaddr */
78#define CONFIG_ENV_OVERWRITE
79
80/* enable I2C */
Wolfgang Denka1be4762008-05-20 16:00:29 +020081#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
83#define CONFIG_SYS_I2C_SLAVE 0x30
wdenke2211742002-11-02 23:30:20 +000084
85
86/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
87#define CONFIG_8260_CLKIN 50000000 /* in Hz */
88
89#define CONFIG_BAUDRATE 115200
90
Jon Loeliger1e8100f2007-07-04 22:33:23 -050091
92/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050093 * BOOTP options
94 */
95#define CONFIG_BOOTP_BOOTFILESIZE
96#define CONFIG_BOOTP_BOOTPATH
97#define CONFIG_BOOTP_GATEWAY
98#define CONFIG_BOOTP_HOSTNAME
99
100
101/*
Jon Loeliger1e8100f2007-07-04 22:33:23 -0500102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105
106#undef CONFIG_CMD_KGDB
107
wdenke2211742002-11-02 23:30:20 +0000108
109/* Define this if you want to boot from 0x00000100. If you don't define
110 * this, you will need to program the bootloader to 0xfff00000, and
111 * get the hardware reset config words at 0xfe000000. The simplest
112 * way to do that is to program the bootloader at both addresses.
113 * It is suggested that you just let U-Boot live at 0x00000000.
114 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#define CONFIG_SYS_RSD_BOOT_LOW 1
wdenke2211742002-11-02 23:30:20 +0000116
wdenke2211742002-11-02 23:30:20 +0000117#define CONFIG_BOOTDELAY 5
Wolfgang Denka1be4762008-05-20 16:00:29 +0200118#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
wdenke2211742002-11-02 23:30:20 +0000119#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
120#define CONFIG_NETMASK 255.255.0.0
121
Jon Loeliger1e8100f2007-07-04 22:33:23 -0500122#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000123#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenke2211742002-11-02 23:30:20 +0000124#endif
125
126/*
127 * Miscellaneous configurable options
128 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger1e8100f2007-07-04 22:33:23 -0500130#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000132#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000134#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
136#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
137#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000143
wdenke2211742002-11-02 23:30:20 +0000144/*
145 * Low Level Configuration Settings
146 * (address mappings, register initial values, etc.)
147 * You should know what you are doing if you make changes here.
148 */
149
150/*-----------------------------------------------------------------------
151 * Physical Memory Map
152 */
153#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
154#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
155
156#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
157#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
158
Wolfgang Denka1be4762008-05-20 16:00:29 +0200159#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
160#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
wdenke2211742002-11-02 23:30:20 +0000161
162/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
163/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
164
Wolfgang Denka1be4762008-05-20 16:00:29 +0200165#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
166#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
wdenke2211742002-11-02 23:30:20 +0000167
168/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
169/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
170
171#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
172#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
173
174#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
175#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
176
177#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
178
179#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
180#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
181
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_IMMR PHYS_IMMR
wdenke2211742002-11-02 23:30:20 +0000183
184/*-----------------------------------------------------------------------
185 * Reset Address
186 *
187 * In order to reset the CPU, U-Boot jumps to a special address which
188 * causes a machine check exception. The default address for this is
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
wdenke2211742002-11-02 23:30:20 +0000190 * testing the monitor in RAM using a JTAG debugger.
191 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
wdenke2211742002-11-02 23:30:20 +0000193 * cause a bus error on your hardware.
194 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_RESET_ADDRESS 0x20000000
wdenke2211742002-11-02 23:30:20 +0000196
197/*-----------------------------------------------------------------------
198 * Hard Reset Configuration Words
199 */
200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#if defined(CONFIG_SYS_RSD_BOOT_LOW)
202# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenke2211742002-11-02 23:30:20 +0000203#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0)
205#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
wdenke2211742002-11-02 23:30:20 +0000206
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207/* get the HRCW ISB field from CONFIG_SYS_IMMR */
208#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
209 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
210 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenke2211742002-11-02 23:30:20 +0000211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \
wdenke2211742002-11-02 23:30:20 +0000213 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214 CONFIG_SYS_RSD_HRCW_IMMR |\
wdenk57b2d802003-06-27 21:31:46 +0000215 HRCW_MMR00 | \
216 HRCW_APPC10 | \
217 HRCW_CS10PC00 | \
218 HRCW_MODCK_H0000 |\
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
wdenke2211742002-11-02 23:30:20 +0000220
221/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_HRCW_SLAVE1 0
223#define CONFIG_SYS_HRCW_SLAVE2 0
224#define CONFIG_SYS_HRCW_SLAVE3 0
225#define CONFIG_SYS_HRCW_SLAVE4 0
226#define CONFIG_SYS_HRCW_SLAVE5 0
227#define CONFIG_SYS_HRCW_SLAVE6 0
228#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000229
230/*-----------------------------------------------------------------------
231 * Definitions for initial stack pointer and data area (in DPRAM)
232 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200234#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200235#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000237
238/*-----------------------------------------------------------------------
239 * Start addresses for the final memory configuration
240 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
242 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
wdenke2211742002-11-02 23:30:20 +0000243 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200244#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X
245#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
246/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */
247#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
248#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
249#define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000250#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
252#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000253
254/*
255 * For booting Linux, the board info and command line data
256 * have to be in the first 8 MB of memory, since this is
257 * the maximum mapped by the Linux kernel during initialization.
258 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000260
261/*-----------------------------------------------------------------------
262 * FLASH and environment organization
263 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
265#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000266
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
268#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000269
270/* turn off NVRAM env feature */
271#undef CONFIG_NVRAM_ENV
272
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200273#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200274#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
275#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000276
277/*-----------------------------------------------------------------------
278 * Cache Configuration
279 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200280#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger1e8100f2007-07-04 22:33:23 -0500281#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000283#endif
284
285/*-----------------------------------------------------------------------
286 * HIDx - Hardware Implementation-dependent Registers 2-11
287 *-----------------------------------------------------------------------
288 * HID0 also contains cache control - initially enable both caches and
289 * invalidate contents, then the final state leaves only the instruction
290 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
291 * but Soft reset does not.
292 *
293 * HID1 has only read-only information - nothing to set.
294 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
296#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
297#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000298
299/*-----------------------------------------------------------------------
300 * RMR - Reset Mode Register
301 *-----------------------------------------------------------------------
302 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_RMR 0
wdenke2211742002-11-02 23:30:20 +0000304
305/*-----------------------------------------------------------------------
306 * BCR - Bus Configuration 4-25
307 *-----------------------------------------------------------------------
308 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_BCR 0x100c0000
wdenke2211742002-11-02 23:30:20 +0000310
311/*-----------------------------------------------------------------------
312 * SIUMCR - SIU Module Configuration 4-31
313 *-----------------------------------------------------------------------
314 */
315
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200316#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
wdenke2211742002-11-02 23:30:20 +0000317 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
318
319/*-----------------------------------------------------------------------
320 * SYPCR - System Protection Control 11-9
321 * SYPCR can only be written once after reset!
322 *-----------------------------------------------------------------------
323 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
324 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
wdenke2211742002-11-02 23:30:20 +0000326 SYPCR_SWRI | SYPCR_SWP)
327
328/*-----------------------------------------------------------------------
329 * TMCNTSC - Time Counter Status and Control 4-40
330 *-----------------------------------------------------------------------
331 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
332 * and enable Time Counter
333 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200334#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
wdenke2211742002-11-02 23:30:20 +0000335
336/*-----------------------------------------------------------------------
337 * PISCR - Periodic Interrupt Status and Control 4-42
338 *-----------------------------------------------------------------------
339 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
340 * Periodic timer
341 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200342#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000343
344/*-----------------------------------------------------------------------
345 * SCCR - System Clock Control 9-8
346 *-----------------------------------------------------------------------
347 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200348#define CONFIG_SYS_SCCR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000349
350/*-----------------------------------------------------------------------
351 * RCCR - RISC Controller Configuration 13-7
352 *-----------------------------------------------------------------------
353 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200354#define CONFIG_SYS_RCCR 0
wdenke2211742002-11-02 23:30:20 +0000355
356/*
357 * Init Memory Controller:
358 */
359
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200360#define CONFIG_SYS_PSDMR 0x494D2452
361#define CONFIG_SYS_LSDMR 0x49492552
wdenke2211742002-11-02 23:30:20 +0000362
363/* Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200364#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V)
365#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000366 ORxG_BCTLD | \
367 ORxG_SCY_5_CLK)
368
369/* DPRAM to the PCI BUS on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200370#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
371#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000372 ORxG_ACS_DIV4)
373
374/* 60x Bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200375#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
376#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000377 ORxS_BPD_4 | \
378 ORxS_ROWST_PBI1_A2 | \
379 ORxS_NUMR_13 | \
380 ORxS_IBID)
381
382/* Virtex-FPGA - Register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200383#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
384#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
wdenk57b2d802003-06-27 21:31:46 +0000385 ORxG_SCY_1_CLK | \
386 ORxG_ACS_DIV2 | \
387 ORxG_CSNT )
wdenke2211742002-11-02 23:30:20 +0000388
389/* local bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200390#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
391#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000392 ORxS_BPD_4 | \
393 ORxS_ROWST_PBI1_A4 | \
394 ORxS_NUMR_13)
395
396/* DPRAM to the Sharc-Bus on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200397#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
398#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000399 ORxG_ACS_DIV4)
400
wdenke2211742002-11-02 23:30:20 +0000401#endif /* __CONFIG_H */