wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> |
| 4 | * |
| 5 | * (C) Copyright 2000 |
| 6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 7 | * Marius Groeger <mgroeger@sysgo.de> |
| 8 | * |
| 9 | * Configuation settings for the R&S Protocol Board board. |
| 10 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 11 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #ifndef __CONFIG_H |
| 15 | #define __CONFIG_H |
| 16 | |
| 17 | /* |
| 18 | * High Level Configuration Options |
| 19 | * (easy to change) |
| 20 | */ |
| 21 | |
| 22 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
| 23 | #define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ |
Jon Loeliger | f5ad378 | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 24 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 25 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_TEXT_BASE 0xff000000 |
Wolfgang Denk | 341e5e7 | 2010-11-28 21:18:58 +0100 | [diff] [blame] | 27 | #define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds" |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 28 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 29 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
| 30 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 31 | /* |
| 32 | * select serial console configuration |
| 33 | * |
| 34 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
| 35 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
| 36 | * for SCC). |
| 37 | * |
| 38 | * if CONFIG_CONS_NONE is defined, then the serial console routines must |
| 39 | * defined elsewhere. |
| 40 | */ |
| 41 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ |
| 42 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 43 | #undef CONFIG_CONS_NONE /* define if console on neither */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 44 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ |
| 45 | |
| 46 | /* |
| 47 | * select ethernet configuration |
| 48 | * |
| 49 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
| 50 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
| 51 | * for FCC) |
| 52 | * |
| 53 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
Jon Loeliger | 2517d97 | 2007-07-09 17:15:49 -0500 | [diff] [blame] | 54 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 55 | */ |
| 56 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ |
| 57 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ |
| 58 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ |
| 59 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ |
| 60 | |
| 61 | #if (CONFIG_ETHER_INDEX == 2) |
| 62 | |
| 63 | /* |
| 64 | * - Rx-CLK is CLK13 |
| 65 | * - Tx-CLK is CLK14 |
| 66 | * - Select bus for bd/buffers (see 28-13) |
| 67 | * - Enable Full Duplex in FSMR |
| 68 | */ |
Mike Frysinger | 109de97 | 2011-10-17 05:38:58 +0000 | [diff] [blame] | 69 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
| 70 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | # define CONFIG_SYS_CPMFCR_RAMTYPE (0) |
| 72 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 73 | |
| 74 | #endif /* CONFIG_ETHER_INDEX */ |
| 75 | |
| 76 | |
| 77 | /* allow to overwrite serial and ethaddr */ |
| 78 | #define CONFIG_ENV_OVERWRITE |
| 79 | |
| 80 | /* enable I2C */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 81 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 82 | #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ |
| 83 | #define CONFIG_SYS_I2C_SLAVE 0x30 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 84 | |
| 85 | |
| 86 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
| 87 | #define CONFIG_8260_CLKIN 50000000 /* in Hz */ |
| 88 | |
| 89 | #define CONFIG_BAUDRATE 115200 |
| 90 | |
Jon Loeliger | 1e8100f | 2007-07-04 22:33:23 -0500 | [diff] [blame] | 91 | |
| 92 | /* |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 93 | * BOOTP options |
| 94 | */ |
| 95 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 96 | #define CONFIG_BOOTP_BOOTPATH |
| 97 | #define CONFIG_BOOTP_GATEWAY |
| 98 | #define CONFIG_BOOTP_HOSTNAME |
| 99 | |
| 100 | |
| 101 | /* |
Jon Loeliger | 1e8100f | 2007-07-04 22:33:23 -0500 | [diff] [blame] | 102 | * Command line configuration. |
| 103 | */ |
| 104 | #include <config_cmd_default.h> |
| 105 | |
| 106 | #undef CONFIG_CMD_KGDB |
| 107 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 108 | |
| 109 | /* Define this if you want to boot from 0x00000100. If you don't define |
| 110 | * this, you will need to program the bootloader to 0xfff00000, and |
| 111 | * get the hardware reset config words at 0xfe000000. The simplest |
| 112 | * way to do that is to program the bootloader at both addresses. |
| 113 | * It is suggested that you just let U-Boot live at 0x00000000. |
| 114 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | #define CONFIG_SYS_RSD_BOOT_LOW 1 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 116 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 117 | #define CONFIG_BOOTDELAY 5 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 118 | #define CONFIG_BOOTARGS "devfs=mount root=ramfs" |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 119 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5a |
| 120 | #define CONFIG_NETMASK 255.255.0.0 |
| 121 | |
Jon Loeliger | 1e8100f | 2007-07-04 22:33:23 -0500 | [diff] [blame] | 122 | #if defined(CONFIG_CMD_KGDB) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 123 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 124 | #endif |
| 125 | |
| 126 | /* |
| 127 | * Miscellaneous configurable options |
| 128 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Jon Loeliger | 1e8100f | 2007-07-04 22:33:23 -0500 | [diff] [blame] | 130 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 132 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 134 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 135 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 136 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 137 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 138 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ |
| 140 | #define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 141 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 143 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 144 | /* |
| 145 | * Low Level Configuration Settings |
| 146 | * (address mappings, register initial values, etc.) |
| 147 | * You should know what you are doing if you make changes here. |
| 148 | */ |
| 149 | |
| 150 | /*----------------------------------------------------------------------- |
| 151 | * Physical Memory Map |
| 152 | */ |
| 153 | #define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ |
| 154 | #define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ |
| 155 | |
| 156 | #define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ |
| 157 | #define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ |
| 158 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 159 | #define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ |
| 160 | #define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 161 | |
| 162 | /*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ |
| 163 | /*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ |
| 164 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 165 | #define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ |
| 166 | #define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 167 | |
| 168 | /*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ |
| 169 | /*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ |
| 170 | |
| 171 | #define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ |
| 172 | #define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 |
| 173 | |
| 174 | #define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ |
| 175 | #define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ |
| 176 | |
| 177 | #define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ |
| 178 | |
| 179 | #define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ |
| 180 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ |
| 181 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | #define CONFIG_SYS_IMMR PHYS_IMMR |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 183 | |
| 184 | /*----------------------------------------------------------------------- |
| 185 | * Reset Address |
| 186 | * |
| 187 | * In order to reset the CPU, U-Boot jumps to a special address which |
| 188 | * causes a machine check exception. The default address for this is |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 190 | * testing the monitor in RAM using a JTAG debugger. |
| 191 | * |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 193 | * cause a bus error on your hardware. |
| 194 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #define CONFIG_SYS_RESET_ADDRESS 0x20000000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 196 | |
| 197 | /*----------------------------------------------------------------------- |
| 198 | * Hard Reset Configuration Words |
| 199 | */ |
| 200 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | #if defined(CONFIG_SYS_RSD_BOOT_LOW) |
| 202 | # define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 203 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 204 | # define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0) |
| 205 | #endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 206 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | /* get the HRCW ISB field from CONFIG_SYS_IMMR */ |
| 208 | #define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ |
| 209 | ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ |
| 210 | ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 211 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 212 | #define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 213 | HRCW_DPPC11 | \ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | CONFIG_SYS_RSD_HRCW_IMMR |\ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 215 | HRCW_MMR00 | \ |
| 216 | HRCW_APPC10 | \ |
| 217 | HRCW_CS10PC00 | \ |
| 218 | HRCW_MODCK_H0000 |\ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 219 | CONFIG_SYS_RSD_HRCW_BOOT_FLAGS) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 220 | |
| 221 | /* no slaves */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 222 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
| 223 | #define CONFIG_SYS_HRCW_SLAVE2 0 |
| 224 | #define CONFIG_SYS_HRCW_SLAVE3 0 |
| 225 | #define CONFIG_SYS_HRCW_SLAVE4 0 |
| 226 | #define CONFIG_SYS_HRCW_SLAVE5 0 |
| 227 | #define CONFIG_SYS_HRCW_SLAVE6 0 |
| 228 | #define CONFIG_SYS_HRCW_SLAVE7 0 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 229 | |
| 230 | /*----------------------------------------------------------------------- |
| 231 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 232 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 233 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 235 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 236 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 237 | |
| 238 | /*----------------------------------------------------------------------- |
| 239 | * Start addresses for the final memory configuration |
| 240 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 241 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 242 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend. |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 243 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 244 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X |
| 245 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH |
| 246 | /*#define CONFIG_SYS_MONITOR_BASE 0x200000 */ |
| 247 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 248 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE |
| 249 | #define CONFIG_SYS_RAMBOOT |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 250 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ |
| 252 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 253 | |
| 254 | /* |
| 255 | * For booting Linux, the board info and command line data |
| 256 | * have to be in the first 8 MB of memory, since this is |
| 257 | * the maximum mapped by the Linux kernel during initialization. |
| 258 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 260 | |
| 261 | /*----------------------------------------------------------------------- |
| 262 | * FLASH and environment organization |
| 263 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 265 | #define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 266 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ |
| 268 | #define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 269 | |
| 270 | /* turn off NVRAM env feature */ |
| 271 | #undef CONFIG_NVRAM_ENV |
| 272 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 273 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 274 | #define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ |
| 275 | #define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 276 | |
| 277 | /*----------------------------------------------------------------------- |
| 278 | * Cache Configuration |
| 279 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
Jon Loeliger | 1e8100f | 2007-07-04 22:33:23 -0500 | [diff] [blame] | 281 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 282 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 283 | #endif |
| 284 | |
| 285 | /*----------------------------------------------------------------------- |
| 286 | * HIDx - Hardware Implementation-dependent Registers 2-11 |
| 287 | *----------------------------------------------------------------------- |
| 288 | * HID0 also contains cache control - initially enable both caches and |
| 289 | * invalidate contents, then the final state leaves only the instruction |
| 290 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, |
| 291 | * but Soft reset does not. |
| 292 | * |
| 293 | * HID1 has only read-only information - nothing to set. |
| 294 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 295 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) |
| 296 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) |
| 297 | #define CONFIG_SYS_HID2 0 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 298 | |
| 299 | /*----------------------------------------------------------------------- |
| 300 | * RMR - Reset Mode Register |
| 301 | *----------------------------------------------------------------------- |
| 302 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 303 | #define CONFIG_SYS_RMR 0 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 304 | |
| 305 | /*----------------------------------------------------------------------- |
| 306 | * BCR - Bus Configuration 4-25 |
| 307 | *----------------------------------------------------------------------- |
| 308 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 309 | #define CONFIG_SYS_BCR 0x100c0000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 310 | |
| 311 | /*----------------------------------------------------------------------- |
| 312 | * SIUMCR - SIU Module Configuration 4-31 |
| 313 | *----------------------------------------------------------------------- |
| 314 | */ |
| 315 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 316 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 317 | SIUMCR_CS10PC01 | SIUMCR_BCTLC01) |
| 318 | |
| 319 | /*----------------------------------------------------------------------- |
| 320 | * SYPCR - System Protection Control 11-9 |
| 321 | * SYPCR can only be written once after reset! |
| 322 | *----------------------------------------------------------------------- |
| 323 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
| 324 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 325 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 326 | SYPCR_SWRI | SYPCR_SWP) |
| 327 | |
| 328 | /*----------------------------------------------------------------------- |
| 329 | * TMCNTSC - Time Counter Status and Control 4-40 |
| 330 | *----------------------------------------------------------------------- |
| 331 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
| 332 | * and enable Time Counter |
| 333 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 334 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 335 | |
| 336 | /*----------------------------------------------------------------------- |
| 337 | * PISCR - Periodic Interrupt Status and Control 4-42 |
| 338 | *----------------------------------------------------------------------- |
| 339 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
| 340 | * Periodic timer |
| 341 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 342 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 343 | |
| 344 | /*----------------------------------------------------------------------- |
| 345 | * SCCR - System Clock Control 9-8 |
| 346 | *----------------------------------------------------------------------- |
| 347 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 348 | #define CONFIG_SYS_SCCR 0x00000000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 349 | |
| 350 | /*----------------------------------------------------------------------- |
| 351 | * RCCR - RISC Controller Configuration 13-7 |
| 352 | *----------------------------------------------------------------------- |
| 353 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 354 | #define CONFIG_SYS_RCCR 0 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 355 | |
| 356 | /* |
| 357 | * Init Memory Controller: |
| 358 | */ |
| 359 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 360 | #define CONFIG_SYS_PSDMR 0x494D2452 |
| 361 | #define CONFIG_SYS_LSDMR 0x49492552 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 362 | |
| 363 | /* Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 364 | #define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V) |
| 365 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 366 | ORxG_BCTLD | \ |
| 367 | ORxG_SCY_5_CLK) |
| 368 | |
| 369 | /* DPRAM to the PCI BUS on the protocol board */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 370 | #define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) |
| 371 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 372 | ORxG_ACS_DIV4) |
| 373 | |
| 374 | /* 60x Bus SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 375 | #define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) |
| 376 | #define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 377 | ORxS_BPD_4 | \ |
| 378 | ORxS_ROWST_PBI1_A2 | \ |
| 379 | ORxS_NUMR_13 | \ |
| 380 | ORxS_IBID) |
| 381 | |
| 382 | /* Virtex-FPGA - Register */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 383 | #define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) |
| 384 | #define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 385 | ORxG_SCY_1_CLK | \ |
| 386 | ORxG_ACS_DIV2 | \ |
| 387 | ORxG_CSNT ) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 388 | |
| 389 | /* local bus SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 390 | #define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) |
| 391 | #define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 392 | ORxS_BPD_4 | \ |
| 393 | ORxS_ROWST_PBI1_A4 | \ |
| 394 | ORxS_NUMR_13) |
| 395 | |
| 396 | /* DPRAM to the Sharc-Bus on the protocol board */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 397 | #define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) |
| 398 | #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 399 | ORxG_ACS_DIV4) |
| 400 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 401 | #endif /* __CONFIG_H */ |