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Stefan Roesec443fe92005-11-22 13:20:42 +01001/*
Stefan Roesefd637932006-03-17 10:28:24 +01002 * (C) Copyright 2005-2006
Stefan Roesec443fe92005-11-22 13:20:42 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesec443fe92005-11-22 13:20:42 +01008 */
9
10/************************************************************************
11 * board/config_p3p440.h - configuration for Prodrive P3P440
12 ***********************************************************************/
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*-----------------------------------------------------------------------
18 * High Level Configuration Options
19 *----------------------------------------------------------------------*/
20#define CONFIG_P3P440 1 /* Board is P3P440 */
21#define CONFIG_440GP 1 /* Specifc GP support */
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +020022#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roesec443fe92005-11-22 13:20:42 +010023#define CONFIG_4xx 1 /* ... PPC4xx family */
24#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
25#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020026
27#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
28
Stefan Roesec443fe92005-11-22 13:20:42 +010029#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
30
31/*-----------------------------------------------------------------------
32 * Base addresses -- Note these are effective addresses where the
33 * actual resources get mapped (not physical addresses)
34 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
36#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
37#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
38#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
40#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
Stefan Roesec443fe92005-11-22 13:20:42 +010041
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
Stefan Roesec443fe92005-11-22 13:20:42 +010043
44/*-----------------------------------------------------------------------
45 * Initial RAM & stack pointer (placed in internal SRAM)
46 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020048#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Stefan Roesec443fe92005-11-22 13:20:42 +010049
Wolfgang Denk0191e472010-10-26 14:34:52 +020050#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesec443fe92005-11-22 13:20:42 +010052
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
54#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
Stefan Roesec443fe92005-11-22 13:20:42 +010055
56/*-----------------------------------------------------------------------
57 * DDR SDRAM
58 *----------------------------------------------------------------------*/
59#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
Stefan Roesefd637932006-03-17 10:28:24 +010060#define CONFIG_SDRAM_ECC /* enable ECC support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_SDRAM_TABLE { \
Stefan Roesefd637932006-03-17 10:28:24 +010062 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
63 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
Stefan Roesec443fe92005-11-22 13:20:42 +010064
65/*-----------------------------------------------------------------------
66 * Serial Port
67 *----------------------------------------------------------------------*/
Stefan Roese3ddce572010-09-20 16:05:31 +020068#define CONFIG_CONS_INDEX 1 /* Use UART0 */
69#define CONFIG_SYS_NS16550
70#define CONFIG_SYS_NS16550_SERIAL
71#define CONFIG_SYS_NS16550_REG_SIZE 1
72#define CONFIG_SYS_NS16550_CLK get_serial_clock()
73
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roesec443fe92005-11-22 13:20:42 +010075#define CONFIG_BAUDRATE 115200
76
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roesec443fe92005-11-22 13:20:42 +010078 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
79 57600, 115200, 230400, 460800, 921600 }
80
81/*-----------------------------------------------------------------------
82 * I2C
83 *----------------------------------------------------------------------*/
Dirk Eibach42b204f2013-04-25 02:40:01 +000084#define CONFIG_SYS_I2C
85#define CONFIG_SYS_I2C_PPC4XX
86#define CONFIG_SYS_I2C_PPC4XX_CH0
87#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
88#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
89#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
Stefan Roesec443fe92005-11-22 13:20:42 +010090
91/*-----------------------------------------------------------------------
92 * I2C RTC
93 *----------------------------------------------------------------------*/
94#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
95
96/*-----------------------------------------------------------------------
97 * I2C EEPROM (PCF8594C) for environment
98 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
100#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roesec443fe92005-11-22 13:20:42 +0100101/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
103#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
Stefan Roesec443fe92005-11-22 13:20:42 +0100104 /* 8 byte page write mode using */
105 /* last 3 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
Stefan Roesec443fe92005-11-22 13:20:42 +0100107
108/*-----------------------------------------------------------------------
109 * Default configuration (environment varibles...)
110 *----------------------------------------------------------------------*/
111#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +0100112 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roesec443fe92005-11-22 13:20:42 +0100113 "echo"
114
115#undef CONFIG_BOOTARGS
116
117#define CONFIG_EXTRA_ENV_SETTINGS \
118 "netdev=eth0\0" \
119 "hostname=p3p440\0" \
120 "nfsargs=setenv bootargs root=/dev/nfs rw " \
121 "nfsroot=${serverip}:${rootpath}\0" \
122 "ramargs=setenv bootargs root=/dev/ram rw\0" \
123 "addip=setenv bootargs ${bootargs} " \
124 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
125 ":${hostname}:${netdev}:off panic=1\0" \
126 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
127 "flash_nfs=run nfsargs addip addtty;" \
128 "bootm ${kernel_addr}\0" \
129 "flash_self=run ramargs addip addtty;" \
130 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
131 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200132 "bootm\0" \
Stefan Roesec443fe92005-11-22 13:20:42 +0100133 "rootpath=/opt/eldk/ppc_4xx\0" \
134 "bootfile=/tftpboot/p3p440/uImage\0" \
135 "kernel_addr=ff800000\0" \
136 "ramdisk_addr=ff810000\0" \
137 "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
138 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
139 "cp.b 100000 fffc0000 40000;" \
140 "setenv filesize;saveenv\0" \
Detlev Zundel406e5782008-03-06 16:45:53 +0100141 "upd=run load update\0" \
Stefan Roeseefef95b2006-04-01 13:41:03 +0200142 "unlock=yes\0" \
Stefan Roesec443fe92005-11-22 13:20:42 +0100143 ""
144#define CONFIG_BOOTCOMMAND "run net_nfs"
145
146#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
147
148#define CONFIG_BAUDRATE 115200
149
150#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roesec443fe92005-11-22 13:20:42 +0100152
Ben Warren3a918a62008-10-27 23:50:15 -0700153#define CONFIG_PPC4xx_EMAC
Stefan Roesec443fe92005-11-22 13:20:42 +0100154#define CONFIG_MII 1 /* MII PHY management */
155#define CONFIG_PHY_ADDR 0x1c /* PHY address */
156#define CONFIG_HAS_ETH1
157#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roesec443fe92005-11-22 13:20:42 +0100159
160#define CONFIG_NETCONSOLE /* include NetConsole support */
161
Stefan Roesec443fe92005-11-22 13:20:42 +0100162
Jon Loeligeraa2d2c22007-07-04 22:33:17 -0500163/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500164 * BOOTP options
165 */
166#define CONFIG_BOOTP_BOOTFILESIZE
167#define CONFIG_BOOTP_BOOTPATH
168#define CONFIG_BOOTP_GATEWAY
169#define CONFIG_BOOTP_HOSTNAME
170
171
172/*
Jon Loeligeraa2d2c22007-07-04 22:33:17 -0500173 * Command line configuration.
174 */
175#include <config_cmd_default.h>
176
177#define CONFIG_CMD_ASKENV
178#define CONFIG_CMD_DATE
179#define CONFIG_CMD_DHCP
180#define CONFIG_CMD_DIAG
181#define CONFIG_CMD_ELF
182#define CONFIG_CMD_I2C
183#define CONFIG_CMD_IRQ
184#define CONFIG_CMD_MII
185#define CONFIG_CMD_NET
186#define CONFIG_CMD_NFS
187#define CONFIG_CMD_PCI
188#define CONFIG_CMD_PING
189#define CONFIG_CMD_REGINFO
190#define CONFIG_CMD_EEPROM
191#define CONFIG_CMD_SNTP
192
Stefan Roesec443fe92005-11-22 13:20:42 +0100193
194#undef CONFIG_WATCHDOG /* watchdog disabled */
195
196/*-----------------------------------------------------------------------
197 * Miscellaneous configurable options
198 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligeraa2d2c22007-07-04 22:33:17 -0500200#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roesec443fe92005-11-22 13:20:42 +0100202#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roesec443fe92005-11-22 13:20:42 +0100204#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
206#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
207#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roesec443fe92005-11-22 13:20:42 +0100208
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
210#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roesec443fe92005-11-22 13:20:42 +0100211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
213#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roesec443fe92005-11-22 13:20:42 +0100214
Stefan Roesec443fe92005-11-22 13:20:42 +0100215#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
216#define CONFIG_LOOPW 1 /* enable loopw command */
217#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
218#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
219
220/*-----------------------------------------------------------------------
221 * PCI stuff
222 *----------------------------------------------------------------------*/
223/* General PCI */
224#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000225#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Stefan Roesec443fe92005-11-22 13:20:42 +0100226#define CONFIG_PCI_PNP /* do pci plug-and-play */
227#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Stefan Roesec443fe92005-11-22 13:20:42 +0100229
230/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
Stefan Roesec443fe92005-11-22 13:20:42 +0100232
233#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
234
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
236#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roesec443fe92005-11-22 13:20:42 +0100237
238/*-----------------------------------------------------------------------
239 * External Bus Controller (EBC) Setup
240 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241#define CONFIG_SYS_FLASH0 0xFF800000
242#define CONFIG_SYS_FLASH1 0xFF000000
243#define CONFIG_SYS_FLASH2 0xFE800000
244#define CONFIG_SYS_FLASH3 0xFE000000
245#define CONFIG_SYS_USB 0xF0000000
Stefan Roesec443fe92005-11-22 13:20:42 +0100246
247/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_EBC_PB0AP 0x03050200
249#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roesec443fe92005-11-22 13:20:42 +0100250
251/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252#define CONFIG_SYS_EBC_PB1AP 0x03050200
253#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roesec443fe92005-11-22 13:20:42 +0100254
255/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#define CONFIG_SYS_EBC_PB2AP 0x03050200
257#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roesec443fe92005-11-22 13:20:42 +0100258
259/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_EBC_PB3AP 0x03050200
261#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roesec443fe92005-11-22 13:20:42 +0100262
263/* Memory Bank 7 (USB controller) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_EBC_PB7AP 0x02015000
265#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
Stefan Roesec443fe92005-11-22 13:20:42 +0100266
267/*-----------------------------------------------------------------------
268 * FLASH related
269 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200271#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roesec443fe92005-11-22 13:20:42 +0100272
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Stefan Roesec443fe92005-11-22 13:20:42 +0100274
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200275#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
276#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roesec443fe92005-11-22 13:20:42 +0100277
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
279#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roesec443fe92005-11-22 13:20:42 +0100280
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200281#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
282#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roesefd637932006-03-17 10:28:24 +0100283
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
285#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roesec443fe92005-11-22 13:20:42 +0100286
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200287#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roesec443fe92005-11-22 13:20:42 +0100288
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200289#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200290#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200291#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roesec443fe92005-11-22 13:20:42 +0100292
293/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200294#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
295#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roesec443fe92005-11-22 13:20:42 +0100296
297/*
298 * For booting Linux, the board info and command line data
299 * have to be in the first 8 MB of memory, since this is
300 * the maximum mapped by the Linux kernel during initialization.
301 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200302#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roesec443fe92005-11-22 13:20:42 +0100303
Jon Loeligeraa2d2c22007-07-04 22:33:17 -0500304#if defined(CONFIG_CMD_KGDB)
Stefan Roesec443fe92005-11-22 13:20:42 +0100305#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Stefan Roesec443fe92005-11-22 13:20:42 +0100306#endif
307#endif /* __CONFIG_H */