blob: 87c06389b44c39b4a9d2c6770c3a208c2edc4e63 [file] [log] [blame]
Heiko Schochera772a162008-08-19 10:08:49 +02001/*
2 * (C) Copyright 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schochera772a162008-08-19 10:08:49 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
16#define CONFIG_8260 1
17#define CONFIG_MPC8260 1
18#define CONFIG_MUAS3001 1
19
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xFF000000
21
Heiko Schochera772a162008-08-19 10:08:49 +020022#define CONFIG_CPM2 1 /* Has a CPM2 */
23
24/* Do boardspecific init */
25#define CONFIG_BOARD_EARLY_INIT_R 1
26
Heiko Schocher4ddfb852008-09-08 10:20:19 +020027/* enable Watchdog */
28#define CONFIG_WATCHDOG 1
29
Heiko Schochera772a162008-08-19 10:08:49 +020030/*
31 * Select serial console configuration
32 *
33 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
34 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
35 * for SCC).
36 */
37#define CONFIG_CONS_ON_SMC /* Console is on SMC */
38#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
39#undef CONFIG_CONS_NONE /* It's not on external UART */
40#if defined(CONFIG_MUAS_DEV_BOARD)
41#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
42#else
43#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
44#endif
45
46/*
47 * Select ethernet configuration
48 *
49 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
50 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
51 * SCC, 1-3 for FCC)
52 *
53 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
54 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
55 * must be unset.
56 */
57#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
58#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
59#undef CONFIG_ETHER_NONE /* No external Ethernet */
60
61#define CONFIG_ETHER_INDEX 1
62#define CONFIG_ETHER_ON_FCC1
Marcel Ziswilerf0c8d422009-09-11 07:50:33 -040063#define CONFIG_HAS_ETH0
Heiko Schochera772a162008-08-19 10:08:49 +020064#define FCC_ENET
65
66/*
67 * - Rx-CLK is CLK11
68 * - Tx-CLK is CLK12
69 */
Mike Frysinger109de972011-10-17 05:38:58 +000070# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
71# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
Heiko Schochera772a162008-08-19 10:08:49 +020072/*
73 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
74 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
Heiko Schochera772a162008-08-19 10:08:49 +020076/* know on local Bus */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
Heiko Schochera772a162008-08-19 10:08:49 +020078/*
79 * - Enable Full Duplex in FSMR
80 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
Heiko Schochera772a162008-08-19 10:08:49 +020082
83#define CONFIG_MII /* MII PHY management */
84#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085# define CONFIG_SYS_PHY_ADDR 1
Heiko Schochera772a162008-08-19 10:08:49 +020086/*
87 * GPIO pins used for bit-banged MII communications
88 */
89#define MDIO_PORT 0 /* Port A */
Luigi 'Comio' Mantellini25e30722009-10-10 12:42:22 +020090#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
91 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
92#define MDC_DECLARE MDIO_DECLARE
93
Heiko Schochera772a162008-08-19 10:08:49 +020094
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
96#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
Heiko Schochera772a162008-08-19 10:08:49 +020097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
99#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
100#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schochera772a162008-08-19 10:08:49 +0200101
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
103 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
Heiko Schochera772a162008-08-19 10:08:49 +0200104
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
106 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
Heiko Schochera772a162008-08-19 10:08:49 +0200107
108#define MIIDELAY udelay(1)
109
110#ifndef CONFIG_8260_CLKIN
111#define CONFIG_8260_CLKIN 66000000 /* in Hz */
112#endif
113
114#define CONFIG_BAUDRATE 115200
115
116/*
117 * Command line configuration.
118 */
119#include <config_cmd_default.h>
120
Heiko Schochera6406692008-09-08 10:21:11 +0200121#define CONFIG_CMD_DTT
Heiko Schochera772a162008-08-19 10:08:49 +0200122#define CONFIG_CMD_ECHO
123#define CONFIG_CMD_IMMAP
124#define CONFIG_CMD_MII
125#define CONFIG_CMD_PING
126#define CONFIG_CMD_I2C
127
128/*
129 * Default environment settings
130 */
131#define CONFIG_EXTRA_ENV_SETTINGS \
132 "netdev=eth0\0" \
133 "u-boot_addr_r=100000\0" \
134 "kernel_addr_r=200000\0" \
135 "fdt_addr_r=400000\0" \
136 "rootpath=/opt/eldk/ppc_6xx\0" \
137 "u-boot=muas3001/u-boot.bin\0" \
138 "bootfile=muas3001/uImage\0" \
139 "fdt_file=muas3001/muas3001.dtb\0" \
140 "ramdisk_file=uRamdisk\0" \
141 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
142 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
143 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
144 "prot on ff000000 ff03ffff\0" \
145 "ramargs=setenv bootargs root=/dev/ram rw\0" \
146 "nfsargs=setenv bootargs root=/dev/nfs rw " \
147 "nfsroot=${serverip}:${rootpath}\0" \
148 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
149 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
150 "addip=setenv bootargs ${bootargs} " \
151 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
152 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
153 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
154 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
155 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
156 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \
157 "tftp ${fdt_addr_r} ${fdt_file}; " \
158 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
159 "run ramargs addip; " \
160 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
161 "ramdisk_addr=ff210000\0" \
162 "kernel_addr=ff050000\0" \
163 "fdt_addr=ff200000\0" \
164 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
165 " ${ramdisk_addr} ${fdt_addr}\0" \
166 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
167 " ${ramdisk_file};" \
168 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
169 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
170 " ${bootfile};" \
171 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
172 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
173 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
174 ""
175
176#define CONFIG_BOOTCOMMAND "run net_nfs"
177#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
178
Heiko Schochera772a162008-08-19 10:08:49 +0200179/*
180 * Miscellaneous configurable options
181 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_LONGHELP /* undef to save memory */
Heiko Schochera772a162008-08-19 10:08:49 +0200184#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schochera772a162008-08-19 10:08:49 +0200186#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schochera772a162008-08-19 10:08:49 +0200188#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
190#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
191#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schochera772a162008-08-19 10:08:49 +0200192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
194#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Heiko Schochera772a162008-08-19 10:08:49 +0200195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Heiko Schochera772a162008-08-19 10:08:49 +0200197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schochera772a162008-08-19 10:08:49 +0200199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_SDRAM_BASE 0x00000000
201#define CONFIG_SYS_FLASH_BASE 0xFF000000
202#define CONFIG_SYS_FLASH_SIZE 32
203#define CONFIG_SYS_FLASH_CFI
Heiko Schochera772a162008-08-19 10:08:49 +0200204#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
206#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
Heiko Schochera772a162008-08-19 10:08:49 +0200207
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Heiko Schochera772a162008-08-19 10:08:49 +0200209
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200210#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
212#define CONFIG_SYS_RAMBOOT
Heiko Schochera772a162008-08-19 10:08:49 +0200213#endif
214
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
Heiko Schochera772a162008-08-19 10:08:49 +0200216
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200217#define CONFIG_ENV_IS_IN_FLASH
Heiko Schochera772a162008-08-19 10:08:49 +0200218
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200219#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200220#define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200222#endif /* CONFIG_ENV_IS_IN_FLASH */
Heiko Schochera772a162008-08-19 10:08:49 +0200223
224/*
225 * I2C Bus
226 */
227#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
229#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schochera772a162008-08-19 10:08:49 +0200230
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
Heiko Schochera6406692008-09-08 10:21:11 +0200232/* I2C SYSMON (LM75, AD7414 is almost compatible) */
233#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
234#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_DTT_MAX_TEMP 70
236#define CONFIG_SYS_DTT_LOW_TEMP -30
237#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schochera6406692008-09-08 10:21:11 +0200238
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200239#define CONFIG_SYS_IMMR 0xF0000000
240#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
Heiko Schochera772a162008-08-19 10:08:49 +0200241
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200243#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200244#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schochera772a162008-08-19 10:08:49 +0200246
247/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
Heiko Schochera772a162008-08-19 10:08:49 +0200249
250/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#define CONFIG_SYS_HRCW_SLAVE1 0
252#define CONFIG_SYS_HRCW_SLAVE2 0
253#define CONFIG_SYS_HRCW_SLAVE3 0
254#define CONFIG_SYS_HRCW_SLAVE4 0
255#define CONFIG_SYS_HRCW_SLAVE5 0
256#define CONFIG_SYS_HRCW_SLAVE6 0
257#define CONFIG_SYS_HRCW_SLAVE7 0
Heiko Schochera772a162008-08-19 10:08:49 +0200258
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
260#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schochera772a162008-08-19 10:08:49 +0200261
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Heiko Schochera772a162008-08-19 10:08:49 +0200263#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schochera772a162008-08-19 10:08:49 +0200265#endif
266
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_SYS_HID0_INIT 0
268#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
Heiko Schochera772a162008-08-19 10:08:49 +0200269
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_HID2 0
Heiko Schochera772a162008-08-19 10:08:49 +0200271
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_SIUMCR 0x00200000
273#define CONFIG_SYS_BCR 0x004c0000
274#define CONFIG_SYS_SCCR 0x0
Heiko Schochera772a162008-08-19 10:08:49 +0200275
276/*-----------------------------------------------------------------------
Heiko Schocher4ddfb852008-09-08 10:20:19 +0200277 * SYPCR - System Protection Control 4-35
278 * SYPCR can only be written once after reset!
279 *-----------------------------------------------------------------------
280 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
281 */
282#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocher4ddfb852008-09-08 10:20:19 +0200284 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
285#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200286#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocher4ddfb852008-09-08 10:20:19 +0200287 SYPCR_SWRI|SYPCR_SWP)
288#endif /* CONFIG_WATCHDOG */
289
290/*-----------------------------------------------------------------------
Heiko Schochera772a162008-08-19 10:08:49 +0200291 * RMR - Reset Mode Register 5-5
292 *-----------------------------------------------------------------------
293 * turn on Checkstop Reset Enable
294 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_SYS_RMR 0
Heiko Schochera772a162008-08-19 10:08:49 +0200296
297/*-----------------------------------------------------------------------
298 * TMCNTSC - Time Counter Status and Control 4-40
299 *-----------------------------------------------------------------------
300 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
301 * and enable Time Counter
302 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
Heiko Schochera772a162008-08-19 10:08:49 +0200304
305/*-----------------------------------------------------------------------
306 * PISCR - Periodic Interrupt Status and Control 4-42
307 *-----------------------------------------------------------------------
308 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
309 * Periodic timer
310 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200311#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
Heiko Schochera772a162008-08-19 10:08:49 +0200312
313/*-----------------------------------------------------------------------
314 * RCCR - RISC Controller Configuration 13-7
315 *-----------------------------------------------------------------------
316 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_RCCR 0
Heiko Schochera772a162008-08-19 10:08:49 +0200318
319/*
320 * Init Memory Controller:
321 *
322 * Bank Bus Machine PortSz Device
323 * ---- --- ------- ------ ------
324 * 0 60x GPCM 32 bit FLASH
325 * 1 60x SDRAM 64 bit SDRAM
326 * 4 60x GPCM 16 bit I/O Ctrl
327 *
328 */
329/* Bank 0 - FLASH
330 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200331#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
Heiko Schochera772a162008-08-19 10:08:49 +0200332 BRx_PS_32 |\
333 BRx_MS_GPCM_P |\
334 BRx_V)
335
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200336#define CONFIG_SYS_OR0_PRELIM (0xff000020)
Heiko Schochera772a162008-08-19 10:08:49 +0200337
338/* Bank 1 - 60x bus SDRAM
339 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200340#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
Heiko Schochera772a162008-08-19 10:08:49 +0200341
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200342#define CONFIG_SYS_MPTPR 0x2800
Heiko Schochera772a162008-08-19 10:08:49 +0200343
344/*-----------------------------------------------------------------------------
345 * Address for Mode Register Set (MRS) command
346 *-----------------------------------------------------------------------------
347 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200348#define CONFIG_SYS_MRS_OFFS 0x00000110
349#define CONFIG_SYS_PSRT 0x13
Heiko Schochera772a162008-08-19 10:08:49 +0200350
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200351#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
Heiko Schochera772a162008-08-19 10:08:49 +0200352 BRx_PS_64 |\
353 BRx_MS_SDRAM_P |\
354 BRx_V)
355
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE
Heiko Schochera772a162008-08-19 10:08:49 +0200357
358/* SDRAM initialization values
359*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200360#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schochera772a162008-08-19 10:08:49 +0200361 ORxS_BPD_4 |\
362 ORxS_ROWST_PBI1_A7 |\
363 ORxS_NUMR_12)
364
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200365#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
Heiko Schocher8a0b1d42008-09-08 10:19:36 +0200366
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200367#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocher8a0b1d42008-09-08 10:19:36 +0200368 ORxS_BPD_4 |\
369 ORxS_ROWST_PBI1_A4 |\
370 ORxS_NUMR_12)
371
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200372#define CONFIG_SYS_PSDMR_BIG 0x014f36a3
Heiko Schochera772a162008-08-19 10:08:49 +0200373
374/* IO on CS4 initialization values
375*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200376#define CONFIG_SYS_IO_BASE 0xc0000000
377#define CONFIG_SYS_IO_SIZE 1
Heiko Schochera772a162008-08-19 10:08:49 +0200378
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200379#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
Heiko Schocher50dd21c2008-09-10 11:15:28 +0200380 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
Heiko Schochera772a162008-08-19 10:08:49 +0200381
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200382#define CONFIG_SYS_OR4_PRELIM (0xfff80020)
Heiko Schochera772a162008-08-19 10:08:49 +0200383
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200384#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
Heiko Schochera772a162008-08-19 10:08:49 +0200385
386/* pass open firmware flat tree */
387#define CONFIG_OF_LIBFDT 1
388#define CONFIG_OF_BOARD_SETUP 1
389
Heiko Schochera772a162008-08-19 10:08:49 +0200390#define OF_TBCLK (bd->bi_busfreq / 4)
391#if defined(CONFIG_MUAS_DEV_BOARD)
392#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
393#else
394#define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
395#endif
396
397#endif /* __CONFIG_H */