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Mark Jonas35a398a2008-03-10 11:37:10 +01001/*
2 * Configuation settings for MPR2
3 *
4 * Copyright (C) 2008
5 * Mark Jonas <mark.jonas@de.bosch.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Mark Jonas35a398a2008-03-10 11:37:10 +01008 */
9
10#ifndef __MPR2_H
11#define __MPR2_H
12
13/* Supported commands */
Mike Frysinger78dcaf42009-01-28 19:08:14 -050014#define CONFIG_CMD_SAVEENV
Mark Jonas35a398a2008-03-10 11:37:10 +010015#define CONFIG_CMD_CACHE
16#define CONFIG_CMD_MEMORY
17#define CONFIG_CMD_FLASH
18
19/* Default environment variables */
20#define CONFIG_BAUDRATE 115200
21#define CONFIG_BOOTARGS "console=ttySC0,115200"
Joe Hershbergere4da2482011-10-13 13:03:48 +000022#define CONFIG_BOOTFILE "/boot/zImage"
Mark Jonas35a398a2008-03-10 11:37:10 +010023#define CONFIG_LOADADDR 0x8E000000
24#define CONFIG_VERSION_VARIABLE
25
26/* CPU and platform */
27#define CONFIG_SH 1
28#define CONFIG_SH3 1
29#define CONFIG_CPU_SH7720 1
30#define CONFIG_MPR2 1
31
32/* U-Boot internals */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
35#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
36#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
37#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
38#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
39#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
40#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
41#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
42#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Mark Jonas35a398a2008-03-10 11:37:10 +010043
Nobuhiro Iwamatsub6e30692011-01-17 21:13:49 +090044#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
45
Mark Jonas35a398a2008-03-10 11:37:10 +010046/* Memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047#define CONFIG_SYS_SDRAM_BASE 0x8C000000
48#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
49#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
50#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Mark Jonas35a398a2008-03-10 11:37:10 +010051
52/* Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020054#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#define CONFIG_SYS_FLASH_EMPTY_INFO
56#define CONFIG_SYS_FLASH_BASE 0xA0000000
57#define CONFIG_SYS_MAX_FLASH_SECT 256
58#define CONFIG_SYS_MAX_FLASH_BANKS 1
59#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020060#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020061#define CONFIG_ENV_SECT_SIZE (128 * 1024)
62#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
64#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
65#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Mark Jonas35a398a2008-03-10 11:37:10 +010066
67/* Clocks */
68#define CONFIG_SYS_CLK_FREQ 24000000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090069#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
70#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +020071#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
Mark Jonas35a398a2008-03-10 11:37:10 +010072
73/* UART */
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020074#define CONFIG_SCIF_CONSOLE 1
Mark Jonas35a398a2008-03-10 11:37:10 +010075#define CONFIG_CONS_SCIF0 1
76
77#endif /* __MPR2_H */