Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> |
| 3 | * (C) Copyright 2009, DAVE Srl <www.dave.eu> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 6 | * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * MECP5123 board configuration file |
| 12 | */ |
| 13 | |
| 14 | #ifndef __CONFIG_H |
| 15 | #define __CONFIG_H |
| 16 | |
| 17 | #define CONFIG_MECP5123 1 |
| 18 | /* |
| 19 | * Memory map for the MECP5123 board: |
| 20 | * |
| 21 | * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) |
| 22 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) |
| 23 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) |
| 24 | * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB) |
| 25 | * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * High Level Configuration Options |
| 30 | */ |
| 31 | #define CONFIG_E300 1 /* E300 Family */ |
| 32 | #define CONFIG_MPC512X 1 /* MPC512X family */ |
| 33 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 34 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 35 | |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 36 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
| 37 | |
| 38 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ |
| 39 | #define CONFIG_MISC_INIT_R |
| 40 | |
| 41 | #define CONFIG_SYS_IMMR 0x80000000 |
| 42 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) |
| 43 | |
| 44 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 45 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
| 46 | |
| 47 | /* |
| 48 | * DDR Setup - manually set all parameters as there's no SPD etc. |
| 49 | */ |
| 50 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
| 51 | |
| 52 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ |
| 53 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
Anatolij Gustschin | 4c6d349 | 2010-04-24 19:27:08 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 55 | |
Anatolij Gustschin | 007a817 | 2010-04-24 19:27:07 +0200 | [diff] [blame] | 56 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
| 57 | |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 58 | /* DDR Controller Configuration |
| 59 | * |
| 60 | * SYS_CFG: |
| 61 | * [31:31] MDDRC Soft Reset: Diabled |
| 62 | * [30:30] DRAM CKE pin: Enabled |
| 63 | * [29:29] DRAM CLK: Enabled |
| 64 | * [28:28] Command Mode: Enabled (For initialization only) |
| 65 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] |
| 66 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] |
| 67 | * [20:19] Read Test: DON'T USE |
| 68 | * [18:18] Self Refresh: Enabled |
| 69 | * [17:17] 16bit Mode: Disabled |
| 70 | * [16:13] Ready Delay: 2 |
| 71 | * [12:12] Half DQS Delay: Disabled |
| 72 | * [11:11] Quarter DQS Delay: Disabled |
| 73 | * [10:08] Write Delay: 2 |
| 74 | * [07:07] Early ODT: Disabled |
| 75 | * [06:06] On DIE Termination: Disabled |
| 76 | * [05:05] FIFO Overflow Clear: DON'T USE here |
| 77 | * [04:04] FIFO Underflow Clear: DON'T USE here |
| 78 | * [03:03] FIFO Overflow Pending: DON'T USE here |
| 79 | * [02:02] FIFO Underlfow Pending: DON'T USE here |
| 80 | * [01:01] FIFO Overlfow Enabled: Enabled |
| 81 | * [00:00] FIFO Underflow Enabled: Enabled |
| 82 | * TIME_CFG0 |
| 83 | * [31:16] DRAM Refresh Time: 0 CSB clocks |
| 84 | * [15:8] DRAM Command Time: 0 CSB clocks |
| 85 | * [07:00] DRAM Precharge Time: 0 CSB clocks |
| 86 | * TIME_CFG1 |
| 87 | * [31:26] DRAM tRFC: |
| 88 | * [25:21] DRAM tWR1: |
| 89 | * [20:17] DRAM tWRT1: |
| 90 | * [16:11] DRAM tDRR: |
| 91 | * [10:05] DRAM tRC: |
| 92 | * [04:00] DRAM tRAS: |
| 93 | * TIME_CFG2 |
| 94 | * [31:28] DRAM tRCD: |
| 95 | * [27:23] DRAM tFAW: |
| 96 | * [22:19] DRAM tRTW1: |
| 97 | * [18:15] DRAM tCCD: |
| 98 | * [14:10] DRAM tRTP: |
| 99 | * [09:05] DRAM tRP: |
| 100 | * [04:00] DRAM tRPA |
| 101 | */ |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 102 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 |
| 103 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 104 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 |
| 105 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 106 | |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 107 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
| 108 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 |
| 109 | #define CONFIG_SYS_DDRCMD_EM2 0x01020000 |
| 110 | #define CONFIG_SYS_DDRCMD_EM3 0x01030000 |
| 111 | #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 |
| 112 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 114 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 115 | |
| 116 | /* DDR Priority Manager Configuration */ |
| 117 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
| 118 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 |
| 119 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 |
| 120 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC |
| 121 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA |
| 122 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 |
| 123 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 |
| 124 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 |
| 125 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 |
| 126 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 |
| 127 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 |
| 128 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 |
| 129 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 |
| 130 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa |
| 131 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa |
| 132 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 |
| 133 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 |
| 134 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 |
| 135 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 |
| 136 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 |
| 137 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 |
| 138 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 |
| 139 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 |
| 140 | |
| 141 | /* |
| 142 | * NOR FLASH on the Local Bus |
| 143 | */ |
| 144 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 145 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| 146 | |
| 147 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */ |
| 148 | #define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */ |
| 149 | |
| 150 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 151 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 152 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
| 153 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ |
| 154 | |
| 155 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 156 | |
| 157 | /* |
| 158 | * NAND FLASH |
Wolfgang Denk | b6e99b4 | 2009-06-14 20:58:50 +0200 | [diff] [blame] | 159 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 160 | */ |
| 161 | #define CONFIG_CMD_NAND |
| 162 | #define CONFIG_NAND_MPC5121_NFC |
| 163 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 165 | |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 166 | /* |
| 167 | * Configuration parameters for MPC5121 NAND driver |
| 168 | */ |
| 169 | #define CONFIG_FSL_NFC_WIDTH 1 |
| 170 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 |
| 171 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 |
| 172 | #define CONFIG_FSL_NFC_CHIPS 1 |
| 173 | |
| 174 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
| 175 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ |
| 176 | |
Anatolij Gustschin | ca625ee | 2013-02-08 00:03:44 +0000 | [diff] [blame] | 177 | /* Initialize Local Window for NOR FLASH access */ |
| 178 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
| 179 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE |
| 180 | |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 181 | /* ALE active low, data size 4bytes */ |
| 182 | #define CONFIG_SYS_CS0_CFG 0x05051150 |
| 183 | |
| 184 | /* Use not alternative CS timing */ |
| 185 | #define CONFIG_SYS_CS_ALETIMING 0x00000000 |
| 186 | |
| 187 | /* ALE active low, data size 4bytes */ |
| 188 | #define CONFIG_SYS_CS1_CFG 0x1f1f3090 |
| 189 | #define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */ |
| 190 | #define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */ |
Anatolij Gustschin | ca625ee | 2013-02-08 00:03:44 +0000 | [diff] [blame] | 191 | /* Initialize Local Window for VPC3 access */ |
| 192 | #define CONFIG_SYS_CS1_START CONFIG_SYS_VPC3_BASE |
| 193 | #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_VPC3_SIZE |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 194 | |
| 195 | /* Use SRAM for initial stack */ |
| 196 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 197 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 198 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 201 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */ |
| 204 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */ |
| 205 | |
| 206 | /* |
| 207 | * Serial Port |
| 208 | */ |
| 209 | #define CONFIG_CONS_INDEX 1 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 210 | |
| 211 | /* |
| 212 | * Serial console configuration |
| 213 | */ |
| 214 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ |
Marek Vasut | e79aa90 | 2012-09-16 16:07:24 +0200 | [diff] [blame] | 215 | #define CONFIG_SYS_PSC3 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 216 | #if CONFIG_PSC_CONSOLE != 3 |
| 217 | #error CONFIG_PSC_CONSOLE must be 3 |
| 218 | #endif |
| 219 | #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ |
| 220 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 221 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 222 | |
| 223 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE |
| 224 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR |
| 225 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE |
| 226 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR |
| 227 | |
Anatolij Gustschin | c936642 | 2013-02-08 00:03:45 +0000 | [diff] [blame] | 228 | /* |
| 229 | * Clocks in use |
| 230 | */ |
| 231 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ |
| 232 | CLOCK_SCCR1_LPC_EN | \ |
| 233 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ |
| 234 | CLOCK_SCCR1_PSCFIFO_EN | \ |
| 235 | CLOCK_SCCR1_DDR_EN | \ |
| 236 | CLOCK_SCCR1_FEC_EN | \ |
| 237 | CLOCK_SCCR1_NFC_EN | \ |
| 238 | CLOCK_SCCR1_PCI_EN | \ |
| 239 | CLOCK_SCCR1_TPR_EN) |
| 240 | |
| 241 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ |
| 242 | CLOCK_SCCR2_I2C_EN) |
| 243 | |
| 244 | |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 245 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 246 | /* Use the HUSH parser */ |
| 247 | #define CONFIG_SYS_HUSH_PARSER |
| 248 | #ifdef CONFIG_SYS_HUSH_PARSER |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 249 | #endif |
| 250 | |
| 251 | /* I2C */ |
| 252 | #define CONFIG_HARD_I2C /* I2C with hardware support */ |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 253 | #define CONFIG_I2C_MULTI_BUS |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 254 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ |
| 255 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ |
| 256 | |
| 257 | /* |
| 258 | * IIM - IC Identification Module |
| 259 | */ |
Benoît Thébaudeau | 8ac3711 | 2013-04-23 10:17:42 +0000 | [diff] [blame] | 260 | #undef CONFIG_FSL_IIM |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 261 | |
| 262 | /* |
| 263 | * EEPROM configuration |
| 264 | */ |
| 265 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ |
| 266 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ |
| 267 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ |
| 268 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ |
| 269 | #define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */ |
| 270 | |
| 271 | /* |
| 272 | * Ethernet configuration |
| 273 | */ |
| 274 | #define CONFIG_MPC512x_FEC 1 |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 275 | #define CONFIG_PHY_ADDR 0x1 |
| 276 | #define CONFIG_MII 1 /* MII PHY management */ |
| 277 | #define CONFIG_FEC_AN_TIMEOUT 1 |
| 278 | #define CONFIG_HAS_ETH0 |
| 279 | |
| 280 | /* |
| 281 | * Configure on-board RTC |
| 282 | */ |
| 283 | #define CONFIG_SYS_RTC_BUS_NUM 0x01 |
| 284 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 |
| 285 | #define CONFIG_RTC_RX8025 |
| 286 | |
| 287 | /* |
| 288 | * Environment |
| 289 | */ |
| 290 | #define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */ |
| 291 | #define CONFIG_ENV_SIZE 0x1000 |
| 292 | #define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */ |
| 293 | |
| 294 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 295 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 296 | |
| 297 | #include <config_cmd_default.h> |
| 298 | |
| 299 | #define CONFIG_CMD_ASKENV |
| 300 | #define CONFIG_CMD_DHCP |
| 301 | #define CONFIG_CMD_I2C |
| 302 | #define CONFIG_CMD_MII |
| 303 | #define CONFIG_CMD_NFS |
| 304 | #define CONFIG_CMD_PING |
| 305 | #define CONFIG_CMD_REGINFO |
| 306 | #define CONFIG_CMD_EEPROM |
| 307 | #define CONFIG_CMD_DATE |
| 308 | #undef CONFIG_CMD_FUSE |
| 309 | #undef CONFIG_CMD_IDE |
| 310 | #undef CONFIG_CMD_EXT2 |
| 311 | #define CONFIG_CMD_FAT |
| 312 | #define CONFIG_CMD_JFFS2 |
| 313 | #define CONFIG_CMD_ELF |
| 314 | #define CONFIG_DOS_PARTITION |
| 315 | |
| 316 | /* |
| 317 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. |
| 318 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set |
| 319 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer |
| 320 | * to chapter 36 of the MPC5121e Reference Manual. |
| 321 | */ |
| 322 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
| 323 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
| 324 | |
| 325 | /* |
| 326 | * Miscellaneous configurable options |
| 327 | */ |
| 328 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 329 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 330 | |
| 331 | #ifdef CONFIG_CMD_KGDB |
| 332 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 333 | #else |
| 334 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 335 | #endif |
| 336 | |
| 337 | /* Print Buffer Size */ |
| 338 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 339 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 340 | /* max number of command args */ |
| 341 | #define CONFIG_SYS_MAXARGS 32 |
| 342 | /* Boot Argument Buffer Size */ |
| 343 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 344 | |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 345 | /* |
| 346 | * For booting Linux, the board info and command line data |
Ira W. Snyder | c5a22d0 | 2010-09-10 15:42:32 -0700 | [diff] [blame] | 347 | * have to be in the first 256 MB of memory, since this is |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 348 | * the maximum mapped by the Linux kernel during initialization. |
| 349 | */ |
Ira W. Snyder | c5a22d0 | 2010-09-10 15:42:32 -0700 | [diff] [blame] | 350 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Linux initial memory map */ |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 351 | |
| 352 | /* Cache Configuration */ |
| 353 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
| 354 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 355 | #ifdef CONFIG_CMD_KGDB |
| 356 | #define CONFIG_SYS_CACHELINE_SHIFT 5 |
| 357 | #endif |
| 358 | |
| 359 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 360 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
| 361 | #define CONFIG_SYS_HID2 HID2_HBE |
| 362 | |
| 363 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 364 | |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 365 | #ifdef CONFIG_CMD_KGDB |
| 366 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 367 | #endif |
| 368 | |
| 369 | /* |
| 370 | * Environment Configuration |
| 371 | */ |
| 372 | #define CONFIG_TIMESTAMP |
| 373 | |
| 374 | #define CONFIG_HOSTNAME mecp512x |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 375 | #define CONFIG_BOOTFILE "/tftpboot/mecp512x/uImage" |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 376 | #define CONFIG_ROOTPATH "/tftpboot/mecp512x/target_root" |
Stefan Roese | abbd0da | 2009-06-09 11:50:40 +0200 | [diff] [blame] | 377 | |
| 378 | #define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */ |
| 379 | |
| 380 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
| 381 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
| 382 | |
| 383 | #define CONFIG_PREBOOT "echo;" \ |
| 384 | "echo Welcome to MECP5123" \ |
| 385 | "echo" |
| 386 | |
| 387 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 388 | "u-boot_addr_r=200000\0" \ |
| 389 | "kernel_addr_r=600000\0" \ |
| 390 | "fdt_addr_r=880000\0" \ |
| 391 | "ramdisk_addr_r=900000\0" \ |
| 392 | "u-boot_addr=FFF00000\0" \ |
| 393 | "kernel_addr=FFC40000\0" \ |
| 394 | "fdt_addr=FFEC0000\0" \ |
| 395 | "ramdisk_addr=FC040000\0" \ |
| 396 | "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \ |
| 397 | "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \ |
| 398 | "bootfile=/tftpboot/mecp512x/uImage\0" \ |
| 399 | "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \ |
| 400 | "rootpath=/tftpboot/mecp512x/target_root\n" \ |
| 401 | "netdev=eth0\0" \ |
| 402 | "consdev=ttyPSC0\0" \ |
| 403 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 404 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 405 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 406 | "addip=setenv bootargs ${bootargs} " \ |
| 407 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 408 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 409 | "addtty=setenv bootargs ${bootargs} " \ |
| 410 | "console=${consdev},${baudrate}\0" \ |
| 411 | "flash_nfs=run nfsargs addip addtty;" \ |
| 412 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
| 413 | "flash_self=run ramargs addip addtty;" \ |
| 414 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
| 415 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ |
| 416 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
| 417 | "run nfsargs addip addtty;" \ |
| 418 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
| 419 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ |
| 420 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ |
| 421 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
| 422 | "run ramargs addip addtty;" \ |
| 423 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
| 424 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
| 425 | "update=protect off ${u-boot_addr} +${filesize};" \ |
| 426 | "era ${u-boot_addr} +${filesize};" \ |
| 427 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ |
| 428 | "upd=run load update\0" \ |
| 429 | "" |
| 430 | |
| 431 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 432 | |
| 433 | #define CONFIG_OF_LIBFDT |
| 434 | #define CONFIG_OF_BOARD_SETUP |
| 435 | |
| 436 | #define OF_CPU "PowerPC,5121@0" |
| 437 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" |
| 438 | #define OF_TBCLK (bd->bi_busfreq / 4) |
| 439 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
| 440 | |
| 441 | #endif /* __CONFIG_H */ |