Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
| 3 | * Copyright (C) 2012 Renesas Solutions Corp. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __KZM9G_H |
| 9 | #define __KZM9G_H |
| 10 | |
| 11 | #undef DEBUG |
| 12 | |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 13 | #define CONFIG_RMOBILE |
| 14 | #define CONFIG_SH73A0 |
| 15 | #define CONFIG_KZM_A9_GT |
| 16 | #define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" |
| 17 | #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G |
| 18 | |
| 19 | #include <asm/arch/rmobile.h> |
| 20 | |
| 21 | #define CONFIG_ARCH_CPU_INIT |
| 22 | #define CONFIG_DISPLAY_CPUINFO |
| 23 | #define CONFIG_DISPLAY_BOARDINFO |
| 24 | #define CONFIG_BOARD_EARLY_INIT_F |
Nobuhiro Iwamatsu | e56b137 | 2012-07-27 11:40:13 +0900 | [diff] [blame] | 25 | #define CONFIG_OF_LIBFDT |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 26 | |
| 27 | #include <config_cmd_default.h> |
| 28 | #define CONFIG_CMDLINE_TAG |
| 29 | #define CONFIG_SETUP_MEMORY_TAGS |
| 30 | #define CONFIG_INITRD_TAG |
| 31 | #define CONFIG_DOS_PARTITION |
| 32 | #define CONFIG_CMD_FAT |
| 33 | #define CONFIG_CMD_BOOTZ |
| 34 | |
Tetsuyuki Kobayashi | 238ce70 | 2012-07-19 16:16:08 +0000 | [diff] [blame] | 35 | #define CONFIG_BAUDRATE 115200 |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 36 | #define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 37 | #define CONFIG_BOOTDELAY 3 |
| 38 | |
| 39 | #define CONFIG_VERSION_VARIABLE |
| 40 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 41 | |
| 42 | /* MEMORY */ |
| 43 | #define KZM_SDRAM_BASE (0x40000000) |
| 44 | #define PHYS_SDRAM KZM_SDRAM_BASE |
| 45 | #define PHYS_SDRAM_SIZE (512 * 1024 * 1024) |
| 46 | #define CONFIG_NR_DRAM_BANKS (1) |
| 47 | |
| 48 | /* NOR Flash */ |
| 49 | #define KZM_FLASH_BASE (0x00000000) |
| 50 | #define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) |
| 51 | #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) |
| 52 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) |
| 53 | #define CONFIG_SYS_MAX_FLASH_SECT (512) |
| 54 | |
| 55 | /* prompt */ |
| 56 | #define CONFIG_SYS_LONGHELP |
Tetsuyuki Kobayashi | 8c131a1 | 2012-07-05 01:43:52 +0000 | [diff] [blame] | 57 | #define CONFIG_SYS_PROMPT "KZM-A9-GT# " |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 58 | #define CONFIG_SYS_CBSIZE 256 |
| 59 | #define CONFIG_SYS_PBSIZE 256 |
| 60 | #define CONFIG_SYS_MAXARGS 16 |
| 61 | #define CONFIG_SYS_BARGSIZE 512 |
| 62 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
| 63 | |
| 64 | /* SCIF */ |
| 65 | #define CONFIG_SCIF_CONSOLE |
| 66 | #define CONFIG_CONS_SCIF4 |
| 67 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET |
| 68 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
| 69 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
| 70 | |
| 71 | #define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) |
| 72 | #define CONFIG_SYS_MEMTEST_END \ |
| 73 | (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) |
| 74 | #undef CONFIG_SYS_ALT_MEMTEST |
| 75 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
| 76 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
| 77 | |
| 78 | #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ |
| 79 | #define CONFIG_SYS_INIT_RAM_SIZE (0x10000) |
| 80 | #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) |
| 81 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 82 | CONFIG_SYS_INIT_RAM_SIZE - \ |
| 83 | GENERATED_GBL_DATA_SIZE) |
Tetsuyuki Kobayashi | 6a8c515 | 2012-07-05 01:43:44 +0000 | [diff] [blame] | 84 | #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) |
| 85 | #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) |
| 86 | #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 87 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
| 88 | |
| 89 | #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) |
| 90 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
| 91 | #define CONFIG_SYS_GBL_DATA_SIZE (256) |
| 92 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
| 93 | |
| 94 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
| 95 | #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 |
| 96 | |
| 97 | /* FLASH */ |
| 98 | #define CONFIG_FLASH_CFI_DRIVER |
| 99 | #define CONFIG_SYS_FLASH_CFI |
| 100 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
| 101 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 102 | #define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ |
| 103 | #define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE |
| 104 | #define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE |
| 105 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
| 106 | |
| 107 | /* Timeout for Flash erase operations (in ms) */ |
| 108 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
| 109 | /* Timeout for Flash write operations (in ms) */ |
| 110 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
| 111 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
| 112 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
| 113 | /* Timeout for Flash clear lock bit operations (in ms) */ |
| 114 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
| 115 | |
| 116 | #undef CONFIG_SYS_FLASH_PROTECTION |
| 117 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
| 118 | #define CONFIG_ENV_IS_IN_FLASH |
| 119 | |
| 120 | /* GPIO / PFC */ |
| 121 | #define CONFIG_SH_GPIO_PFC |
| 122 | |
| 123 | /* Clock */ |
Nobuhiro Iwamatsu | 8c00236 | 2012-08-03 13:56:52 +0900 | [diff] [blame] | 124 | #define CONFIG_GLOBAL_TIMER |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 125 | #define CONFIG_SYS_CLK_FREQ (48000000) |
| 126 | #define CONFIG_SYS_CPU_CLK (1196000000) |
Nobuhiro Iwamatsu | adbaef5 | 2013-09-30 10:30:40 +0900 | [diff] [blame] | 127 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 128 | #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 129 | |
| 130 | /* Ether */ |
| 131 | #define CONFIG_NET_MULTI |
| 132 | #define CONFIG_CMD_PING |
| 133 | #define CONFIG_CMD_DHCP |
| 134 | #define CONFIG_SMC911X |
| 135 | #define CONFIG_SMC911X_BASE (0x10000000) |
| 136 | #define CONFIG_SMC911X_32_BIT |
Tetsuyuki Kobayashi | 3d74327 | 2012-07-25 18:24:18 +0000 | [diff] [blame] | 137 | #define CONFIG_NFS_TIMEOUT 10000UL |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 138 | |
| 139 | /* I2C */ |
| 140 | #define CONFIG_CMD_I2C |
Nobuhiro Iwamatsu | 1224010 | 2013-10-29 13:33:51 +0900 | [diff] [blame] | 141 | #define CONFIG_SYS_I2C |
| 142 | #define CONFIG_SYS_I2C_SH |
| 143 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 |
| 144 | #define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 |
| 145 | #define CONFIG_SYS_I2C_SH_SPEED0 100000 |
| 146 | #define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 |
| 147 | #define CONFIG_SYS_I2C_SH_SPEED1 100000 |
| 148 | #define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 |
| 149 | #define CONFIG_SYS_I2C_SH_SPEED2 100000 |
| 150 | #define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 |
| 151 | #define CONFIG_SYS_I2C_SH_SPEED3 100000 |
| 152 | #define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 |
| 153 | #define CONFIG_SYS_I2C_SH_SPEED4 100000 |
Tetsuyuki Kobayashi | cc4283c | 2012-09-13 19:07:56 +0000 | [diff] [blame] | 154 | #define CONFIG_SH_I2C_8BIT |
Nobuhiro Iwamatsu | 1224010 | 2013-10-29 13:33:51 +0900 | [diff] [blame] | 155 | #define CONFIG_SH_I2C_DATA_HIGH 4 |
| 156 | #define CONFIG_SH_I2C_DATA_LOW 5 |
| 157 | #define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ |
Nobuhiro Iwamatsu | 06d4c6d | 2012-06-21 14:55:07 +0900 | [diff] [blame] | 158 | |
| 159 | #endif /* __KZM9G_H */ |