blob: 811ff995e260be6017c70b787d8aa572ca36611d [file] [log] [blame]
Larry Johnsonaecb3a32007-12-22 15:16:25 -05001/*
Larry Johnson52ab1812009-01-28 15:30:37 -05002 * (C) Copyright 2007-2009
Larry Johnsonaecb3a32007-12-22 15:16:25 -05003 * Larry Johnson, lrj@acm.org
4 *
5 * (C) Copyright 2006-2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * (C) Copyright 2006
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
11 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Larry Johnsonaecb3a32007-12-22 15:16:25 -050013 */
14
Larry Johnsonf35b86b2008-01-18 21:49:05 -050015/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -050016 * korat.h - configuration for Korat board
Larry Johnsonf35b86b2008-01-18 21:49:05 -050017 */
Larry Johnsonaecb3a32007-12-22 15:16:25 -050018#ifndef __CONFIG_H
19#define __CONFIG_H
20
Larry Johnsonf35b86b2008-01-18 21:49:05 -050021/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -050022 * High Level Configuration Options
Larry Johnsonf35b86b2008-01-18 21:49:05 -050023 */
24#define CONFIG_440EPX 1 /* Specific PPC440EPx */
25#define CONFIG_4xx 1 /* ... PPC4xx family */
Larry Johnsonaecb3a32007-12-22 15:16:25 -050026#define CONFIG_SYS_CLK_FREQ 33333333
27
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020028#ifdef CONFIG_KORAT_PERMANENT
29#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
30#else
31#define CONFIG_SYS_TEXT_BASE 0xF7F60000
32#endif
33
Larry Johnsonf35b86b2008-01-18 21:49:05 -050034#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
35#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Larry Johnsonaecb3a32007-12-22 15:16:25 -050036
Larry Johnsonf35b86b2008-01-18 21:49:05 -050037/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -050038 * Manufacturer's information serial EEPROM parameters
Larry Johnsonf35b86b2008-01-18 21:49:05 -050039 */
40#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
Larry Johnson67682672008-03-17 11:10:35 -050041#define MAN_INFO_FIELD 2
42#define MAN_INFO_LENGTH 9
Larry Johnsonaecb3a32007-12-22 15:16:25 -050043#define MAN_MAC_ADDR_FIELD 3
Larry Johnson67682672008-03-17 11:10:35 -050044#define MAN_MAC_ADDR_LENGTH 12
Larry Johnsonaecb3a32007-12-22 15:16:25 -050045
Larry Johnsonf35b86b2008-01-18 21:49:05 -050046/*
47 * Base addresses -- Note these are effective addresses where the actual
48 * resources get mapped (not physical addresses).
49 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
51#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
Larry Johnsonaecb3a32007-12-22 15:16:25 -050052
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
54#define CONFIG_SYS_FLASH0_SIZE 0x01000000
55#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
56#define CONFIG_SYS_FLASH1_TOP 0xF8000000
57#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
58#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
59#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
Wolfgang Denk0708bc62010-10-07 21:51:12 +020060#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
62#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
63#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
64#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Stefan Roese8e538be2009-11-12 12:00:49 +010065#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
Larry Johnsonaecb3a32007-12-22 15:16:25 -050066
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_USB2D0_BASE 0xe0000100
68#define CONFIG_SYS_USB_DEVICE 0xe0000000
69#define CONFIG_SYS_USB_HOST 0xe0000400
70#define CONFIG_SYS_CPLD_BASE 0xc0000000
Larry Johnsonaecb3a32007-12-22 15:16:25 -050071
Larry Johnsonf35b86b2008-01-18 21:49:05 -050072/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -050073 * Initial RAM & stack pointer
Larry Johnsonf35b86b2008-01-18 21:49:05 -050074 */
Larry Johnsonaecb3a32007-12-22 15:16:25 -050075/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#undef CONFIG_SYS_INIT_RAM_DCACHE
77#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020078#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk0191e472010-10-26 14:34:52 +020079#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidmanf969a682010-09-20 08:51:53 +020080#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Larry Johnsonaecb3a32007-12-22 15:16:25 -050081
Larry Johnsonf35b86b2008-01-18 21:49:05 -050082/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -050083 * Serial Port
Larry Johnsonf35b86b2008-01-18 21:49:05 -050084 */
Stefan Roese3ddce572010-09-20 16:05:31 +020085#define CONFIG_CONS_INDEX 1 /* Use UART0 */
86#define CONFIG_SYS_NS16550
87#define CONFIG_SYS_NS16550_SERIAL
88#define CONFIG_SYS_NS16550_REG_SIZE 1
89#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Larry Johnsonaecb3a32007-12-22 15:16:25 -050091#define CONFIG_BAUDRATE 115200
Larry Johnsonaecb3a32007-12-22 15:16:25 -050092
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_BAUDRATE_TABLE \
Larry Johnsonaecb3a32007-12-22 15:16:25 -050094 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
95
Larry Johnsonf35b86b2008-01-18 21:49:05 -050096/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -050097 * Environment
Larry Johnsonf35b86b2008-01-18 21:49:05 -050098 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020099#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500100
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500101/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500102 * FLASH related
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500103 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200105#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Larry Johnson67682672008-03-17 11:10:35 -0500106#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500109
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
111#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500112
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
114#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
117#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
120#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500121
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200122#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200124#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500125
Larry Johnson67682672008-03-17 11:10:35 -0500126/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200127#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
128#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500129
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500130/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500131 * DDR SDRAM
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500132 */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500133#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
134#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
135#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
136#define CONFIG_DDR_ECC /* Use ECC when available */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500137#define SPD_EEPROM_ADDRESS {0x50}
138#define CONFIG_PROG_SDRAM_TLB
Larry Johnson52ab1812009-01-28 15:30:37 -0500139#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
140 /* per 440EPx Errata CHIP_11 */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500141
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500142/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500143 * I2C
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500144 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000145#define CONFIG_SYS_I2C
146#define CONFIG_SYS_I2C_PPC4XX
147#define CONFIG_SYS_I2C_PPC4XX_CH0
148#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
149#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500150
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_I2C_MULTI_EEPROMS
152#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
153#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
154#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
155#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500156
157/* I2C RTC */
158#define CONFIG_RTC_M41T60 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500160
161/* I2C SYSMON (LM73) */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500162#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
163#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_DTT_MAX_TEMP 70
165#define CONFIG_SYS_DTT_MIN_TEMP -30
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500166
167#define CONFIG_PREBOOT "echo;" \
Larry Johnson52ab1812009-01-28 15:30:37 -0500168 "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500169 "echo"
170
171#undef CONFIG_BOOTARGS
172
173/* Setup some board specific values for the default environment variables */
174#define CONFIG_HOSTNAME korat
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500175
Larry Johnson67682672008-03-17 11:10:35 -0500176/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
Larry Johnsonfc391002008-06-14 16:53:02 -0400177#define CONFIG_EXTRA_ENV_SETTINGS \
Larry Johnson52ab1812009-01-28 15:30:37 -0500178 "u_boot=korat/u-boot.bin\0" \
179 "load=tftp 200000 ${u_boot}\0" \
180 "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
181 "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
182 "F7F60000 F7FBFFFF\0" \
183 "upd=run load update\0" \
184 "bootfile=korat/uImage\0" \
185 "dtb=korat/korat.dtb\0" \
186 "kernel_addr=F4000000\0" \
187 "ramdisk_addr=F4400000\0" \
188 "dtb_addr=F41E0000\0" \
189 "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
190 "cp.b ${fileaddr} F4000000 ${filesize}\0" \
191 "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
192 "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
193 "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
194 "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
195 "${dtb}\0" \
196 "rd_size=73728\0" \
197 "ramargs=setenv bootargs root=/dev/ram rw " \
198 "ramdisk_size=${rd_size}\0" \
199 "usbdev=sda1\0" \
200 "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
201 "rootpath=/opt/eldk/ppc_4xxFP\0" \
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500202 "netdev=eth0\0" \
203 "nfsargs=setenv bootargs root=/dev/nfs rw " \
204 "nfsroot=${serverip}:${rootpath}\0" \
Larry Johnson52ab1812009-01-28 15:30:37 -0500205 "pciclk=33\0" \
206 "addide=setenv bootargs ${bootargs} ide=reverse " \
207 "idebus=${pciclk}\0" \
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500208 "addip=setenv bootargs ${bootargs} " \
209 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
210 ":${hostname}:${netdev}:off panic=1\0" \
211 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Larry Johnson52ab1812009-01-28 15:30:37 -0500212 "flash_cf=run usbargs addide addip addtty; " \
213 "bootm ${kernel_addr} - ${dtb_addr}\0" \
214 "flash_nfs=run nfsargs addide addip addtty; " \
215 "bootm ${kernel_addr} - ${dtb_addr}\0" \
216 "flash_self=run ramargs addip addtty; " \
217 "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500218 ""
Larry Johnson52ab1812009-01-28 15:30:37 -0500219
220#define CONFIG_BOOTCOMMAND "run flash_cf"
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500221
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500222#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500223
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500224#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500226
Ben Warren3a918a62008-10-27 23:50:15 -0700227#define CONFIG_PPC4xx_EMAC
Larry Johnsonfc391002008-06-14 16:53:02 -0400228#define CONFIG_IBM_EMAC4_V4 1
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500229#define CONFIG_MII 1 /* MII PHY management */
230#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500231#define CONFIG_PHY_DYNAMIC_ANEG 1
232
Larry Johnson67682672008-03-17 11:10:35 -0500233#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500234#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
235
236#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200237#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500238 /* buffers & descriptors */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500239#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500240#define CONFIG_PHY1_ADDR 3
241
242/* USB */
243#define CONFIG_USB_OHCI
244#define CONFIG_USB_STORAGE
245
246/* Comment this out to enable USB 1.1 device */
247#define USB_2_0_DEVICE
248
249/* Partitions */
250#define CONFIG_MAC_PARTITION
251#define CONFIG_DOS_PARTITION
252#define CONFIG_ISO_PARTITION
253
254/*
255 * BOOTP options
256 */
257#define CONFIG_BOOTP_BOOTFILESIZE
258#define CONFIG_BOOTP_BOOTPATH
259#define CONFIG_BOOTP_GATEWAY
260#define CONFIG_BOOTP_HOSTNAME
261#define CONFIG_BOOTP_SUBNETMASK
262
263/*
264 * Command line configuration.
265 */
266#include <config_cmd_default.h>
267
268#define CONFIG_CMD_ASKENV
269#define CONFIG_CMD_DATE
270#define CONFIG_CMD_DHCP
271#define CONFIG_CMD_DTT
272#define CONFIG_CMD_DIAG
273#define CONFIG_CMD_EEPROM
274#define CONFIG_CMD_ELF
275#define CONFIG_CMD_FAT
276#define CONFIG_CMD_I2C
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500277#define CONFIG_CMD_IRQ
278#define CONFIG_CMD_MII
279#define CONFIG_CMD_NET
280#define CONFIG_CMD_NFS
281#define CONFIG_CMD_PCI
282#define CONFIG_CMD_PING
283#define CONFIG_CMD_REGINFO
284#define CONFIG_CMD_SDRAM
285#define CONFIG_CMD_USB
286
287/* POST support */
Larry Johnson52ab1812009-01-28 15:30:37 -0500288#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
289 CONFIG_SYS_POST_CPU | \
290 CONFIG_SYS_POST_ECC | \
291 CONFIG_SYS_POST_ETHER | \
292 CONFIG_SYS_POST_FPU | \
293 CONFIG_SYS_POST_I2C | \
294 CONFIG_SYS_POST_MEMORY | \
295 CONFIG_SYS_POST_RTC | \
296 CONFIG_SYS_POST_SPR | \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297 CONFIG_SYS_POST_UART)
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500298
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500299#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200300#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500301
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200302#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500303
304#define CONFIG_SUPPORT_VFAT
305
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500306/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500307 * Miscellaneous configurable options
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500308 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_LONGHELP /* undef to save memory */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500310#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200311#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500312#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200313#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500314#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200315#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Wolfgang Denka1be4762008-05-20 16:00:29 +0200316 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
318#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500319
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200320#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
321#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500322
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200323#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
324#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500325
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500326#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
327#define CONFIG_LOOPW 1 /* enable loopw command */
328#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
329#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
330#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500331
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500332/*
Larry Johnson67682672008-03-17 11:10:35 -0500333 * Korat-specific options
334 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200335#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
Larry Johnson67682672008-03-17 11:10:35 -0500336
337/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500338 * PCI stuff
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500339 */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500340/* General PCI */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500341#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000342#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500343#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200344#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500345#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200346#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
347 /* CONFIG_SYS_PCI_MEMBASE */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500348/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#define CONFIG_SYS_PCI_TARGET_INIT
350#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese5d8033e2009-11-12 16:41:09 +0100351#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500352
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
354#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500355
356/*
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500357 * For booting Linux, the board info and command line data have to be in the
358 * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
359 * during initialization.
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500360 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200361#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500362
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500363/*
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500364 * External Bus Controller (EBC) Setup
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500365 */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500366
367/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
369#define CONFIG_SYS_EBC_PB0AP 0x04017300
370#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
371#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
372#define CONFIG_SYS_EBC_PB0AP 0x04017300
373#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
Larry Johnson67682672008-03-17 11:10:35 -0500374#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200375#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
Larry Johnson67682672008-03-17 11:10:35 -0500376#endif
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500377
378/* Memory Bank 1 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200379#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
380#define CONFIG_SYS_EBC_PB1AP 0x04017300
381#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
Larry Johnson67682672008-03-17 11:10:35 -0500382#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200383#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
Larry Johnson67682672008-03-17 11:10:35 -0500384#endif
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500385
386/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200387#define CONFIG_SYS_EBC_PB2AP 0x04017300
388#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500389
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500390/*
Lawrence R. Johnson59890582008-01-03 15:02:02 -0500391 * GPIO Setup
392 *
393 * Korat GPIO usage:
394 *
395 * Init.
396 * Pin Source I/O value Function
397 * ------ ------ --- ----- ---------------------------------
398 * GPIO00 Alt1 I/O x PerAddr07
399 * GPIO01 Alt1 I/O x PerAddr06
400 * GPIO02 Alt1 I/O x PerAddr05
401 * GPIO03 GPIO x x GPIO03 to expansion bus connector
402 * GPIO04 GPIO x x GPIO04 to expansion bus connector
403 * GPIO05 GPIO x x GPIO05 to expansion bus connector
404 * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
405 * GPIO07 Alt1 O x PerCS2 (CPLD)
406 * GPIO08 Alt1 O x PerCS3 to expansion bus connector
407 * GPIO09 Alt1 O x PerCS4 to expansion bus connector
408 * GPIO10 Alt1 O x PerCS5 to expansion bus connector
409 * GPIO11 Alt1 I x PerErr
410 * GPIO12 GPIO O 0 ATMega !Reset
Larry Johnson52ab1812009-01-28 15:30:37 -0500411 * GPIO13 GPIO x x Test Point 2 (TP2)
Lawrence R. Johnson59890582008-01-03 15:02:02 -0500412 * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
413 * GPIO15 GPIO O 0 CPU Run LED !On
414 * GPIO16 Alt1 O x GMC1TxD0
415 * GPIO17 Alt1 O x GMC1TxD1
416 * GPIO18 Alt1 O x GMC1TxD2
417 * GPIO19 Alt1 O x GMC1TxD3
418 * GPIO20 Alt1 I x RejectPkt0
419 * GPIO21 Alt1 I x RejectPkt1
420 * GPIO22 GPIO I x PGOOD_DDR
421 * GPIO23 Alt1 O x SCPD0
422 * GPIO24 Alt1 O x GMC0TxD2
423 * GPIO25 Alt1 O x GMC0TxD3
424 * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
425 * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
426 * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
427 * GPIO29 GPIO I x Test jumper !Present
428 * GPIO30 GPIO I x SFP module #0 !Present
429 * GPIO31 GPIO I x SFP module #1 !Present
430 *
431 * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
432 * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
433 * GPIO34 Alt2 I x !UART1_CTS
434 * GPIO35 Alt2 O x !UART1_RTS
435 * GPIO36 Alt1 I x !UART0_CTS
436 * GPIO37 Alt1 O x !UART0_RTS
437 * GPIO38 Alt2 O x UART1_Tx
438 * GPIO39 Alt2 I x UART1_Rx
439 * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
440 * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
441 * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
442 * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
443 * GPIO44 xxxx x x (grounded through pulldown)
444 * GPIO45 GPIO O 0 PHY #0 Enable
445 * GPIO46 GPIO O 0 PHY #1 Enable
446 * GPIO47 GPIO I x Reset switch !Pressed
447 * GPIO48 GPIO I x Shutdown switch !Pressed
448 * GPIO49 xxxx x x (reserved for trace port)
449 * . . . . .
450 * . . . . .
451 * . . . . .
452 * GPIO63 xxxx x x (reserved for trace port)
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500453 */
Lawrence R. Johnson59890582008-01-03 15:02:02 -0500454
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200455#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
456#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
457#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
458#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
459#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
460#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
461#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
462#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
463#define CONFIG_SYS_GPIO_PHY0_EN 45
464#define CONFIG_SYS_GPIO_PHY1_EN 46
465#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
Lawrence R. Johnson59890582008-01-03 15:02:02 -0500466
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500467/*
Lawrence R. Johnson59890582008-01-03 15:02:02 -0500468 * PPC440 GPIO Configuration
469 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200470#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Lawrence R. Johnson59890582008-01-03 15:02:02 -0500471{ \
472/* GPIO Core 0 */ \
473{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
474{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
475{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
476{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
477{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
478{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
479{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
480{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
481{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
482{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
483{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
484{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
485{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
Larry Johnson52ab1812009-01-28 15:30:37 -0500486{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
Lawrence R. Johnson59890582008-01-03 15:02:02 -0500487{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
488{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
489{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
490{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
491{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
492{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
493{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
494{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
495{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
496{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
497{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
498{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
499{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
500{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
501{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
502{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
503{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
504{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
505}, \
506{ \
507/* GPIO Core 1 */ \
508{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
509{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
510{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
511{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
512{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
513{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
514{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
515{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
516{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
517{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
518{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
519{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
520{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
521{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
522{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
523{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
524{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
525{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
526{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
527{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
528{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
529{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
530{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
531{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
532{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
533{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
534{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
535{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
536{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
537{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
538{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
540} \
541}
542
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500543#if defined(CONFIG_CMD_KGDB)
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500544#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500545#endif
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500546
Larry Johnsonfc391002008-06-14 16:53:02 -0400547/* Pass open firmware flat tree */
548#define CONFIG_OF_LIBFDT 1
549#define CONFIG_OF_BOARD_SETUP 1
550
Larry Johnsonaecb3a32007-12-22 15:16:25 -0500551#endif /* __CONFIG_H */