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Chander Kashyaped2e25a2012-02-05 23:01:47 +00001/*
Hatim RV793ed482012-12-11 00:52:48 +00002 * Copyright (C) 2012 Samsung Electronics
Chander Kashyaped2e25a2012-02-05 23:01:47 +00003 *
Hatim RV793ed482012-12-11 00:52:48 +00004 * Configuration settings for the SAMSUNG EXYNOS5250 board.
Chander Kashyaped2e25a2012-02-05 23:01:47 +00005 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Chander Kashyaped2e25a2012-02-05 23:01:47 +00007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/* High Level Configuration Options */
13#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14#define CONFIG_S5P /* S5P Family */
15#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
Chander Kashyapd4409932013-07-25 18:28:52 +053016#define CONFIG_EXYNOS5250
Chander Kashyaped2e25a2012-02-05 23:01:47 +000017
18#include <asm/arch/cpu.h> /* get chip and board defs */
19
Simon Glasscdf4e972013-03-05 14:39:58 +000020#define CONFIG_SYS_GENERIC_BOARD
Chander Kashyaped2e25a2012-02-05 23:01:47 +000021#define CONFIG_ARCH_CPU_INIT
22#define CONFIG_DISPLAY_CPUINFO
23#define CONFIG_DISPLAY_BOARDINFO
24
Hatim RV793ed482012-12-11 00:52:48 +000025/* Enable fdt support for Exynos5250 */
Hatim RV793ed482012-12-11 00:52:48 +000026#define CONFIG_OF_CONTROL
27#define CONFIG_OF_SEPARATE
28
Simon Glass0843e9e2013-06-11 11:14:51 -070029/* Allow tracing to be enabled */
30#define CONFIG_TRACE
31#define CONFIG_CMD_TRACE
32#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
33#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
34#define CONFIG_TRACE_EARLY
35#define CONFIG_TRACE_EARLY_ADDR 0x50000000
36
Chander Kashyaped2e25a2012-02-05 23:01:47 +000037/* Keep L2 Cache Disabled */
38#define CONFIG_SYS_DCACHE_OFF
39
Vivek Gautamb198e422013-09-14 14:02:50 +053040#define CONFIG_SYS_CACHELINE_SIZE 64
41
Akshay Saraswat150a9db2013-03-20 21:00:57 +000042/* Enable ACE acceleration for SHA1 and SHA256 */
43#define CONFIG_EXYNOS_ACE_SHA
Akshay Saraswatb20d7d62013-03-20 21:00:59 +000044#define CONFIG_SHA_HW_ACCEL
Akshay Saraswat150a9db2013-03-20 21:00:57 +000045
Chander Kashyaped2e25a2012-02-05 23:01:47 +000046#define CONFIG_SYS_SDRAM_BASE 0x40000000
47#define CONFIG_SYS_TEXT_BASE 0x43E00000
48
49/* input clock of PLL: SMDK5250 has 24MHz input clock */
50#define CONFIG_SYS_CLK_FREQ 24000000
51
52#define CONFIG_SETUP_MEMORY_TAGS
53#define CONFIG_CMDLINE_TAG
54#define CONFIG_INITRD_TAG
55#define CONFIG_CMDLINE_EDITING
56
57/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
58#define MACH_TYPE_SMDK5250 3774
59#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
60
61/* Power Down Modes */
62#define S5P_CHECK_SLEEP 0x00000BAD
63#define S5P_CHECK_DIDLE 0xBAD00000
64#define S5P_CHECK_LPA 0xABAD0000
65
66/* Offset for inform registers */
67#define INFORM0_OFFSET 0x800
68#define INFORM1_OFFSET 0x804
69
70/* Size of malloc() pool */
Rajeshwari Shinde418eb7e2012-12-10 01:55:48 +000071#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
Chander Kashyaped2e25a2012-02-05 23:01:47 +000072
73/* select serial console configuration */
Chander Kashyaped2e25a2012-02-05 23:01:47 +000074#define CONFIG_BAUDRATE 115200
75#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
Rajeshwari Shinde5c824332013-06-24 16:47:23 +053076#define CONFIG_SILENT_CONSOLE
Chander Kashyaped2e25a2012-02-05 23:01:47 +000077
Hung-ying Tyana4ed85d2013-05-15 18:27:34 +080078/* Enable keyboard */
79#define CONFIG_CROS_EC /* CROS_EC protocol */
80#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
81#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
82#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
83#define CONFIG_CMD_CROS_EC
84#define CONFIG_KEYBOARD
85
Ajay Kumarf6a62fe2013-01-10 21:06:11 +000086/* Console configuration */
87#define CONFIG_CONSOLE_MUX
88#define CONFIG_SYS_CONSOLE_IS_IN_ENV
89#define EXYNOS_DEVICE_SETTINGS \
Hung-ying Tyana4ed85d2013-05-15 18:27:34 +080090 "stdin=serial,cros-ec-keyb\0" \
Ajay Kumarf6a62fe2013-01-10 21:06:11 +000091 "stdout=serial,lcd\0" \
92 "stderr=serial,lcd\0"
93
94#define CONFIG_EXTRA_ENV_SETTINGS \
95 EXYNOS_DEVICE_SETTINGS
96
Chander Kashyaped2e25a2012-02-05 23:01:47 +000097/* SD/MMC configuration */
98#define CONFIG_GENERIC_MMC
99#define CONFIG_MMC
Jaehoon Chunga38690e2012-04-23 02:36:29 +0000100#define CONFIG_SDHCI
101#define CONFIG_S5P_SDHCI
Amarbb54b752013-04-27 11:42:57 +0530102#define CONFIG_DWMMC
103#define CONFIG_EXYNOS_DWMMC
104#define CONFIG_SUPPORT_EMMC_BOOT
105
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000106
107#define CONFIG_BOARD_EARLY_INIT_F
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530108#define CONFIG_SKIP_LOWLEVEL_INIT
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000109
110/* PWM */
111#define CONFIG_PWM
112
113/* allow to overwrite serial and ethaddr */
114#define CONFIG_ENV_OVERWRITE
115
116/* Command definition*/
117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_PING
120#define CONFIG_CMD_ELF
121#define CONFIG_CMD_MMC
122#define CONFIG_CMD_EXT2
123#define CONFIG_CMD_FAT
Chander Kashyap5ff8061e2012-02-09 01:26:19 +0000124#define CONFIG_CMD_NET
Akshay Saraswatb20d7d62013-03-20 21:00:59 +0000125#define CONFIG_CMD_HASH
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000126
127#define CONFIG_BOOTDELAY 3
128#define CONFIG_ZERO_BOOTDELAY_CHECK
129
Akshay Saraswatc9ba97e2013-02-25 01:13:03 +0000130/* Thermal Management Unit */
131#define CONFIG_EXYNOS_TMU
Akshay Saraswat60e72fa2013-02-25 01:13:05 +0000132#define CONFIG_CMD_DTT
133#define CONFIG_TMU_CMD_DTT
Akshay Saraswatc9ba97e2013-02-25 01:13:03 +0000134
Rajeshwari Shinde8755bb92012-05-14 05:52:05 +0000135/* USB */
136#define CONFIG_CMD_USB
Vivek Gautamc728d142013-09-14 14:02:51 +0530137#define CONFIG_USB_XHCI
138#define CONFIG_USB_XHCI_EXYNOS
139#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
Rajeshwari Shinde8755bb92012-05-14 05:52:05 +0000140#define CONFIG_USB_STORAGE
141
Vivek Gautam681dd832013-01-28 00:39:59 +0000142/* USB boot mode */
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530143#define CONFIG_USB_BOOTING
Vivek Gautam681dd832013-01-28 00:39:59 +0000144#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
145#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
146#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
147
Simon Glass2df1f7a2013-04-12 10:44:58 +0000148/* TPM */
149#define CONFIG_TPM
150#define CONFIG_CMD_TPM
Tom Wai-Hong Tame49fed52013-04-12 11:04:37 +0000151#define CONFIG_TPM_TIS_I2C
152#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
153#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
Simon Glass2df1f7a2013-04-12 10:44:58 +0000154
Chander Kashyap1633dd12012-02-05 23:01:48 +0000155/* MMC SPL */
156#define CONFIG_SPL
157#define COPY_BL2_FNPTR_ADDR 0x02020030
158
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530159#define CONFIG_SPL_LIBCOMMON_SUPPORT
Rajeshwari Shinde507f8922013-10-08 18:42:22 +0530160#define CONFIG_SPL_GPIO_SUPPORT
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530161
Rajeshwari Shindee44ebd02012-07-03 20:02:53 +0000162/* specific .lds file */
Rajeshwari Shinde111591f2013-07-04 12:29:15 +0530163#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
Rajeshwari Shindee44ebd02012-07-03 20:02:53 +0000164#define CONFIG_SPL_TEXT_BASE 0x02023400
Albert ARIBAUD19a053d2013-04-12 05:14:33 +0000165#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
Rajeshwari Shindee44ebd02012-07-03 20:02:53 +0000166
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000167#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
168
169/* Miscellaneous configurable options */
170#define CONFIG_SYS_LONGHELP /* undef to save memory */
171#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000172#define CONFIG_SYS_PROMPT "SMDK5250 # "
173#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
174#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
175#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
176#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
177/* Boot Argument Buffer Size */
178#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
179/* memtest works on */
180#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
181#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
182#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
183
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000184#define CONFIG_RD_LVL
185
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000186#define CONFIG_NR_DRAM_BANKS 8
187#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
188#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
189#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
190#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
191#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
192#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
193#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
194#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
195#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
196#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
197#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
198#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
199#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
200#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
201#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
202#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
203#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
204
205#define CONFIG_SYS_MONITOR_BASE 0x00000000
206
207/* FLASH and environment organization */
208#define CONFIG_SYS_NO_FLASH
209#undef CONFIG_CMD_IMLS
210#define CONFIG_IDENT_STRING " for SMDK5250"
211
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000212#define CONFIG_SYS_MMC_ENV_DEV 0
213
214#define CONFIG_SECURE_BL1_ONLY
215
216/* Secure FW size configuration */
217#ifdef CONFIG_SECURE_BL1_ONLY
218#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
219#else
220#define CONFIG_SEC_FW_SIZE 0
221#endif
222
223/* Configuration of BL1, BL2, ENV Blocks on mmc */
224#define CONFIG_RES_BLOCK_SIZE (512)
225#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
226#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
227#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
228
229#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
230#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
231#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
232
Chander Kashyap1633dd12012-02-05 23:01:48 +0000233/* U-boot copy size from boot Media to DRAM.*/
234#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
235#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
Rajeshwari Shinde9cb48e82012-11-02 01:15:38 +0000236
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530237#define CONFIG_SPI_BOOTING
Rajeshwari Shinde9cb48e82012-11-02 01:15:38 +0000238#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
239#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
240
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000241#define CONFIG_DOS_PARTITION
Amarbb54b752013-04-27 11:42:57 +0530242#define CONFIG_EFI_PARTITION
243#define CONFIG_CMD_PART
244#define CONFIG_PARTITION_UUIDS
245
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000246
247#define CONFIG_IRAM_STACK 0x02050000
248
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530249#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000250
Rajeshwari Shinde1d518e62012-07-23 21:23:55 +0000251/* I2C */
252#define CONFIG_SYS_I2C_INIT_BOARD
Piotr Wilczek58bbd2b2013-11-20 10:43:49 +0100253#define CONFIG_SYS_I2C
Rajeshwari Shinde1d518e62012-07-23 21:23:55 +0000254#define CONFIG_CMD_I2C
Piotr Wilczek58bbd2b2013-11-20 10:43:49 +0100255#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
256#define CONFIG_SYS_I2C_S3C24X0
Rajeshwari Shinde1d518e62012-07-23 21:23:55 +0000257#define CONFIG_I2C_MULTI_BUS
258#define CONFIG_MAX_I2C_NUM 8
Piotr Wilczek58bbd2b2013-11-20 10:43:49 +0100259#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
Simon Glass9f68f8e2012-12-05 14:46:45 +0000260#define CONFIG_I2C_EDID
Rajeshwari Shinde1d518e62012-07-23 21:23:55 +0000261
Rajeshwari Shinde346fe622012-08-24 00:39:24 +0000262/* PMIC */
263#define CONFIG_PMIC
264#define CONFIG_PMIC_I2C
265#define CONFIG_PMIC_MAX77686
266
Hatim RV000b5482012-11-02 01:15:37 +0000267/* SPI */
268#define CONFIG_ENV_IS_IN_SPI_FLASH
269#define CONFIG_SPI_FLASH
Rajeshwari Shinde507f8922013-10-08 18:42:22 +0530270#define CONFIG_ENV_SPI_BASE 0x12D30000
Hatim RV000b5482012-11-02 01:15:37 +0000271
272#ifdef CONFIG_SPI_FLASH
273#define CONFIG_EXYNOS_SPI
274#define CONFIG_CMD_SF
275#define CONFIG_CMD_SPI
276#define CONFIG_SPI_FLASH_WINBOND
Rajeshwari Shindee2036642013-01-22 20:31:57 +0000277#define CONFIG_SPI_FLASH_GIGADEVICE
Hatim RV000b5482012-11-02 01:15:37 +0000278#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
279#define CONFIG_SF_DEFAULT_SPEED 50000000
280#define EXYNOS5_SPI_NUM_CONTROLLERS 5
Simon Glass49e9d2c2013-12-03 16:43:24 -0700281#define CONFIG_OF_SPI
Hatim RV000b5482012-11-02 01:15:37 +0000282#endif
283
284#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
285#define CONFIG_ENV_SPI_MODE SPI_MODE_0
286#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
287#define CONFIG_ENV_SPI_BUS 1
288#define CONFIG_ENV_SPI_MAX_HZ 50000000
289#endif
290
Albert ARIBAUD8f9e08b2012-12-22 11:59:14 +0100291/* PMIC */
Rajeshwari Shinde418eb7e2012-12-10 01:55:48 +0000292#define CONFIG_POWER
293#define CONFIG_POWER_I2C
294#define CONFIG_POWER_MAX77686
Chander Kashyap5ff8061e2012-02-09 01:26:19 +0000295
Chander Kashyap5ff8061e2012-02-09 01:26:19 +0000296/* Ethernet Controllor Driver */
297#ifdef CONFIG_CMD_NET
298#define CONFIG_SMC911X
299#define CONFIG_SMC911X_BASE 0x5000000
300#define CONFIG_SMC911X_16_BIT
301#define CONFIG_ENV_SROM_BANK 1
302#endif /*CONFIG_CMD_NET*/
303
Chander Kashyapd94e1f22012-09-05 00:38:21 +0000304/* Enable PXE Support */
305#ifdef CONFIG_CMD_NET
306#define CONFIG_CMD_PXE
307#define CONFIG_MENU
308#endif
309
Rajeshwari Shinde4453d232012-10-25 19:49:30 +0000310/* Sound */
311#define CONFIG_CMD_SOUND
312#ifdef CONFIG_CMD_SOUND
313#define CONFIG_SOUND
314#define CONFIG_I2S
Rajeshwari Shinde4200a522013-02-14 19:46:16 +0000315#define CONFIG_SOUND_MAX98095
Rajeshwari Shinde4453d232012-10-25 19:49:30 +0000316#define CONFIG_SOUND_WM8994
317#endif
318
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000319/* Enable devicetree support */
320#define CONFIG_OF_LIBFDT
321
Simon Glass9f68f8e2012-12-05 14:46:45 +0000322/* SHA hashing */
323#define CONFIG_CMD_HASH
324#define CONFIG_HASH_VERIFY
325#define CONFIG_SHA1
326#define CONFIG_SHA256
327
Ajay Kumarca67ee22013-01-08 20:42:26 +0000328/* Display */
329#define CONFIG_LCD
Ajay Kumar11575ae2013-01-10 21:06:10 +0000330#ifdef CONFIG_LCD
Ajay Kumarca67ee22013-01-08 20:42:26 +0000331#define CONFIG_EXYNOS_FB
332#define CONFIG_EXYNOS_DP
333#define LCD_XRES 2560
334#define LCD_YRES 1600
335#define LCD_BPP LCD_COLOR16
Ajay Kumar11575ae2013-01-10 21:06:10 +0000336#endif
Ajay Kumarca67ee22013-01-08 20:42:26 +0000337
Akshay Saraswata3e6c192013-03-28 04:32:15 +0000338/* Enable Time Command */
339#define CONFIG_CMD_TIME
340
Chander Kashyaped2e25a2012-02-05 23:01:47 +0000341#endif /* __CONFIG_H */