Macpaul Lin | 80a9b13 | 2011-09-23 16:49:59 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Andes Technology Corporation |
| 3 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Macpaul Lin | 80a9b13 | 2011-09-23 16:49:59 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | #include <asm/arch/ag102.h> |
| 12 | |
| 13 | /* |
| 14 | * CPU and Board Configuration Options |
| 15 | */ |
| 16 | #define CONFIG_ADP_AG102 |
| 17 | |
| 18 | #define CONFIG_USE_INTERRUPT |
| 19 | |
| 20 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 21 | |
| 22 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 23 | #define CONFIG_MEM_REMAP |
| 24 | #endif |
| 25 | |
| 26 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT |
| 27 | #define CONFIG_SYS_TEXT_BASE 0x04200000 |
| 28 | #else |
| 29 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
| 30 | #endif |
| 31 | |
| 32 | /* |
| 33 | * Timer |
| 34 | */ |
Macpaul Lin | 80a9b13 | 2011-09-23 16:49:59 +0800 | [diff] [blame] | 35 | #define CONFIG_SYS_CLK_FREQ (66000000 * 2) |
| 36 | #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ |
| 37 | |
| 38 | /* |
| 39 | * Use Externel CLOCK or PCLK |
| 40 | */ |
| 41 | #undef CONFIG_FTRTC010_EXTCLK |
| 42 | |
| 43 | #ifndef CONFIG_FTRTC010_EXTCLK |
| 44 | #define CONFIG_FTRTC010_PCLK |
| 45 | #endif |
| 46 | |
| 47 | #ifdef CONFIG_FTRTC010_EXTCLK |
| 48 | #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ |
| 49 | #else |
| 50 | #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ |
| 51 | #endif |
| 52 | |
| 53 | #define TIMER_LOAD_VAL 0xffffffff |
| 54 | |
| 55 | /* |
| 56 | * Real Time Clock |
| 57 | */ |
| 58 | #define CONFIG_RTC_FTRTC010 |
| 59 | |
| 60 | /* |
| 61 | * Real Time Clock Divider |
| 62 | * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
| 63 | */ |
| 64 | #define OSC_5MHZ (5*1000000) |
| 65 | #define OSC_CLK (2*OSC_5MHZ) |
| 66 | #define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
| 67 | |
| 68 | /* |
| 69 | * Serial console configuration |
| 70 | */ |
| 71 | |
| 72 | /* FTUART is a high speed NS 16C550A compatible UART */ |
| 73 | #define CONFIG_BAUDRATE 38400 |
| 74 | #define CONFIG_CONS_INDEX 1 |
| 75 | #define CONFIG_SYS_NS16550 |
| 76 | #define CONFIG_SYS_NS16550_SERIAL |
| 77 | #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE |
| 78 | #define CONFIG_SYS_NS16550_REG_SIZE -4 |
| 79 | #define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */ |
| 80 | |
Macpaul Lin | 80a9b13 | 2011-09-23 16:49:59 +0800 | [diff] [blame] | 81 | /* |
| 82 | * Ethernet |
| 83 | */ |
| 84 | #define CONFIG_NET_MULTI |
| 85 | #define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */ |
| 86 | #define CONFIG_SYS_DISCOVER_PHY |
| 87 | #define CONFIG_FTGMAC100 |
| 88 | #define CONFIG_FTGMAC100_EGIGA |
| 89 | |
| 90 | #define CONFIG_BOOTDELAY 3 |
| 91 | |
| 92 | /* |
| 93 | * SD (MMC) controller |
| 94 | */ |
| 95 | #define CONFIG_MMC |
| 96 | #define CONFIG_CMD_MMC |
| 97 | #define CONFIG_GENERIC_MMC |
| 98 | #define CONFIG_DOS_PARTITION |
| 99 | #define CONFIG_FTSDC010 |
| 100 | #define CONFIG_FTSDC010_NUMBER 1 |
| 101 | #define CONFIG_FTSDC010_SDIO |
| 102 | #define CONFIG_CMD_FAT |
| 103 | #define CONFIG_CMD_EXT2 |
| 104 | |
| 105 | /* |
| 106 | * Command line configuration. |
| 107 | */ |
| 108 | #include <config_cmd_default.h> |
| 109 | |
| 110 | #define CONFIG_CMD_CACHE |
| 111 | #define CONFIG_CMD_DATE |
| 112 | #define CONFIG_CMD_PING |
| 113 | #define CONFIG_CMD_IDE |
| 114 | #define CONFIG_CMD_FAT |
| 115 | #define CONFIG_CMD_ELF |
| 116 | |
| 117 | #undef CONFIG_CMD_FLASH |
| 118 | #undef CONFIG_CMD_IMLS |
| 119 | |
| 120 | /* |
| 121 | * PCI |
| 122 | */ |
| 123 | #define CONFIG_PCI |
| 124 | #define CONFIG_FTPCI100 |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 125 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Macpaul Lin | 80a9b13 | 2011-09-23 16:49:59 +0800 | [diff] [blame] | 126 | #define CONFIG_FTPCI100_MEM_BASE 0xa0000000 |
| 127 | #define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */ |
| 128 | #define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */ |
| 129 | #define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50 |
| 130 | |
| 131 | #define CONFIG_PCI_MEM_BUS 0xa0000000 |
| 132 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
| 133 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */ |
| 134 | |
| 135 | #define CONFIG_PCI_IO_BUS 0x90000000 |
| 136 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
| 137 | #define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */ |
| 138 | |
| 139 | /* |
| 140 | * USB |
| 141 | */ |
| 142 | #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) |
| 143 | #if defined(CONFIG_FTPCI100) |
| 144 | #define __io /* enable outl & inl */ |
| 145 | #define CONFIG_CMD_USB |
| 146 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5 |
| 147 | #define CONFIG_USB_STORAGE |
| 148 | #define CONFIG_USB_EHCI |
| 149 | #define CONFIG_PCI_EHCI_DEVICE 0 |
| 150 | #define CONFIG_USB_EHCI_PCI |
| 151 | #define CONFIG_PREBOOT "usb start;" |
| 152 | #endif /* #if defiend(CONFIG_FTPCI100) */ |
| 153 | #endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */ |
| 154 | |
| 155 | /* |
| 156 | * IDE/ATA stuff |
| 157 | */ |
| 158 | #define __io |
| 159 | #define CONFIG_IDE_AHB |
| 160 | #define CONFIG_IDE_FTIDE020 |
| 161 | |
| 162 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 163 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| 164 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
| 165 | #define CONFIG_IDE_PREINIT 1 /* preinit for ide */ |
| 166 | |
| 167 | /* max: 2 IDE busses */ |
| 168 | #define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */ |
| 169 | /* max: 2 drives per IDE bus */ |
| 170 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */ |
| 171 | |
| 172 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE |
| 173 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| 174 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000 |
| 175 | |
| 176 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */ |
| 177 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */ |
| 178 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */ |
| 179 | |
| 180 | #define CONFIG_MAC_PARTITION |
| 181 | #define CONFIG_DOS_PARTITION |
| 182 | #define CONFIG_SUPPORT_VFAT |
| 183 | |
| 184 | /* |
| 185 | * Miscellaneous configurable options |
| 186 | */ |
| 187 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 188 | #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ |
| 189 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 190 | |
| 191 | /* Print Buffer Size */ |
| 192 | #define CONFIG_SYS_PBSIZE \ |
| 193 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 194 | |
| 195 | /* max number of command args */ |
| 196 | #define CONFIG_SYS_MAXARGS 16 |
| 197 | |
| 198 | /* Boot Argument Buffer Size */ |
| 199 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 200 | |
| 201 | /* |
Macpaul Lin | 80a9b13 | 2011-09-23 16:49:59 +0800 | [diff] [blame] | 202 | * Size of malloc() pool |
| 203 | */ |
| 204 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
| 205 | |
| 206 | /* |
| 207 | * size in bytes reserved for initial data |
| 208 | */ |
| 209 | #define CONFIG_SYS_GBL_DATA_SIZE 128 |
| 210 | |
| 211 | /* |
| 212 | * AHB Controller configuration |
| 213 | */ |
| 214 | #define CONFIG_FTAHBC020S |
| 215 | |
| 216 | #ifdef CONFIG_FTAHBC020S |
| 217 | #include <faraday/ftahbc020s.h> |
| 218 | |
| 219 | /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ |
| 220 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 |
| 221 | |
| 222 | /* |
| 223 | * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, |
| 224 | * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote |
| 225 | * in C language. |
| 226 | */ |
| 227 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ |
| 228 | (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ |
| 229 | FTAHBC020S_SLAVE_BSR_SIZE(0xb)) |
| 230 | #endif |
| 231 | |
| 232 | /* |
| 233 | * Watchdog |
| 234 | */ |
| 235 | #define CONFIG_FTWDT010_WATCHDOG |
| 236 | |
| 237 | /* |
| 238 | * PCU Power Control Unit configuration |
| 239 | */ |
| 240 | #define CONFIG_ANDES_PCU |
| 241 | |
| 242 | #ifdef CONFIG_ANDES_PCU |
| 243 | #include <andestech/andes_pcu.h> |
| 244 | |
| 245 | #endif |
| 246 | |
| 247 | /* |
| 248 | * DDR DRAM controller configuration |
| 249 | */ |
| 250 | #define CONFIG_DWCDDR21MCTL |
| 251 | |
| 252 | #ifdef CONFIG_DWCDDR21MCTL |
| 253 | #include <synopsys/dwcddr21mctl.h> |
| 254 | /* DCR: |
| 255 | * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend |
| 256 | * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk |
| 257 | * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks) |
| 258 | * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank) |
| 259 | * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks) |
| 260 | */ |
| 261 | #define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004 |
| 262 | #define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \ |
| 263 | DWCDDR21MCTL_CCR_DFTLM(0x4) | \ |
| 264 | DWCDDR21MCTL_CCR_HOSTEN(0x1)) |
| 265 | |
| 266 | /* 0x04: 0x000020d4 */ |
| 267 | #define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca |
| 268 | |
| 269 | /* 0x08: 0x0000000f */ |
| 270 | #define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f |
| 271 | |
| 272 | /* 0x10: 0x00034812 */ |
| 273 | #define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \ |
| 274 | DWCDDR21MCTL_DRR_TRFPRD(0x0348)) |
| 275 | /* 0x24 */ |
| 276 | #define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0) |
| 277 | |
| 278 | /* 0x4c: 0x00000040 */ |
| 279 | #define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040 |
| 280 | |
| 281 | /* 0x5c: 0x000055CF */ |
| 282 | #define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf |
| 283 | |
| 284 | /* 0xa4: 0x00100000 */ |
| 285 | #define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \ |
| 286 | DWCDDR21MCTL_DTAR_DTROW(0x0100) | \ |
| 287 | DWCDDR21MCTL_DTAR_DTCOL(0x0)) |
| 288 | /* 0x1f0: 0x00000852 */ |
| 289 | #define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \ |
| 290 | DWCDDR21MCTL_MR_CL(0x5) | \ |
| 291 | DWCDDR21MCTL_MR_BL(0x2)) |
| 292 | #endif |
| 293 | |
| 294 | /* |
| 295 | * Physical Memory Map |
| 296 | */ |
| 297 | #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) |
| 298 | #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ |
| 299 | #if defined(CONFIG_MEM_REMAP) |
| 300 | #define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/ |
| 301 | #endif |
| 302 | #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ |
| 303 | #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ |
| 304 | #endif |
| 305 | |
| 306 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| 307 | #define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */ |
| 308 | |
| 309 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 |
| 310 | |
| 311 | #ifdef CONFIG_MEM_REMAP |
| 312 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ |
| 313 | GENERATED_GBL_DATA_SIZE) |
| 314 | #else |
| 315 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ |
| 316 | GENERATED_GBL_DATA_SIZE) |
| 317 | #endif /* CONFIG_MEM_REMAP */ |
| 318 | |
| 319 | /* |
| 320 | * Load address and memory test area should agree with |
| 321 | * board/faraday/a320/config.mk |
| 322 | * Be careful not to overwrite U-boot itself. |
| 323 | */ |
| 324 | #define CONFIG_SYS_LOAD_ADDR 0x0CF00000 |
| 325 | |
| 326 | /* memtest works on 63 MB in DRAM */ |
| 327 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 |
| 328 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) |
| 329 | |
| 330 | /* |
| 331 | * Static memory controller configuration |
| 332 | */ |
| 333 | |
| 334 | /* |
| 335 | * FLASH and environment organization |
| 336 | */ |
| 337 | #define CONFIG_SYS_NO_FLASH |
| 338 | |
| 339 | /* |
| 340 | * Env Storage Settings |
| 341 | */ |
| 342 | #define CONFIG_ENV_IS_NOWHERE |
| 343 | #define CONFIG_ENV_SIZE 4096 |
| 344 | |
| 345 | #endif /* __CONFIG_H */ |