wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003-2004 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. |
| 7 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /* |
| 15 | * Check valid setting of revision define. |
| 16 | * Total5100 and Total5200 Rev.1 are identical except for the processor. |
| 17 | */ |
| 18 | #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) |
| 19 | #error CONFIG_TOTAL5200_REV must be 1 or 2 |
| 20 | #endif |
| 21 | |
| 22 | /* |
| 23 | * High Level Configuration Options |
| 24 | * (easy to change) |
| 25 | */ |
| 26 | |
| 27 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
Detlev Zundel | a414c7a | 2010-03-12 10:01:12 +0100 | [diff] [blame] | 28 | #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 29 | #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ |
| 30 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 31 | /* |
| 32 | * Valid values for CONFIG_SYS_TEXT_BASE are: |
| 33 | * 0xFFF00000 boot high (standard configuration) |
| 34 | * 0xFE000000 boot low |
| 35 | * 0x00100000 boot from RAM (for testing only) |
| 36 | */ |
| 37 | #ifndef CONFIG_SYS_TEXT_BASE |
| 38 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 39 | #endif |
| 40 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 41 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 42 | |
Becky Bruce | 03ea1be | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 43 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 44 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 45 | /* |
| 46 | * Serial console configuration |
| 47 | */ |
| 48 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ |
| 49 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 50 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 51 | |
wdenk | 7dd1329 | 2004-07-11 20:04:51 +0000 | [diff] [blame] | 52 | /* |
| 53 | * Video console |
| 54 | */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 55 | #define CONFIG_VIDEO |
wdenk | 7dd1329 | 2004-07-11 20:04:51 +0000 | [diff] [blame] | 56 | #define CONFIG_VIDEO_SED13806 |
| 57 | #define CONFIG_VIDEO_SED13806_16BPP |
| 58 | |
| 59 | #define CONFIG_CFB_CONSOLE |
| 60 | #define CONFIG_VIDEO_LOGO |
| 61 | /* #define CONFIG_VIDEO_BMP_LOGO */ |
| 62 | #define CONFIG_CONSOLE_EXTRA_INFO |
| 63 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 64 | #define CONFIG_VIDEO_SW_CURSOR |
| 65 | #define CONFIG_SPLASH_SCREEN |
| 66 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 67 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 68 | /* |
| 69 | * PCI Mapping: |
| 70 | * 0x40000000 - 0x4fffffff - PCI Memory |
| 71 | * 0x50000000 - 0x50ffffff - PCI IO Space |
| 72 | */ |
| 73 | #define CONFIG_PCI 1 |
| 74 | #define CONFIG_PCI_PNP 1 |
| 75 | #define CONFIG_PCI_SCAN_SHOW 1 |
TsiChung Liew | 521f97b | 2008-03-30 01:19:06 -0500 | [diff] [blame] | 76 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 77 | |
| 78 | #define CONFIG_PCI_MEM_BUS 0x40000000 |
| 79 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
| 80 | #define CONFIG_PCI_MEM_SIZE 0x10000000 |
| 81 | |
| 82 | #define CONFIG_PCI_IO_BUS 0x50000000 |
| 83 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
| 84 | #define CONFIG_PCI_IO_SIZE 0x01000000 |
| 85 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 86 | #define CONFIG_MII 1 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 87 | #define CONFIG_EEPRO100 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 89 | #define CONFIG_NS8382X 1 |
| 90 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 91 | /* Partitions */ |
| 92 | #define CONFIG_MAC_PARTITION |
| 93 | #define CONFIG_DOS_PARTITION |
| 94 | |
| 95 | /* USB */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 96 | #define CONFIG_USB_OHCI |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 97 | #define CONFIG_USB_STORAGE |
Jon Loeliger | 59cf509 | 2007-07-04 22:31:15 -0500 | [diff] [blame] | 98 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 99 | |
| 100 | /* |
Jon Loeliger | beb9ff4 | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 101 | * BOOTP options |
| 102 | */ |
| 103 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 104 | #define CONFIG_BOOTP_BOOTPATH |
| 105 | #define CONFIG_BOOTP_GATEWAY |
| 106 | #define CONFIG_BOOTP_HOSTNAME |
| 107 | |
| 108 | |
| 109 | /* |
Jon Loeliger | 59cf509 | 2007-07-04 22:31:15 -0500 | [diff] [blame] | 110 | * Command line configuration. |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 111 | */ |
Jon Loeliger | 59cf509 | 2007-07-04 22:31:15 -0500 | [diff] [blame] | 112 | #include <config_cmd_default.h> |
| 113 | |
Detlev Zundel | a414c7a | 2010-03-12 10:01:12 +0100 | [diff] [blame] | 114 | #define CONFIG_CMD_PCI |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 115 | |
Jon Loeliger | 59cf509 | 2007-07-04 22:31:15 -0500 | [diff] [blame] | 116 | #define CONFIG_CMD_BMP |
| 117 | #define CONFIG_CMD_EEPROM |
| 118 | #define CONFIG_CMD_FAT |
| 119 | #define CONFIG_CMD_I2C |
| 120 | #define CONFIG_CMD_IDE |
| 121 | #define CONFIG_CMD_PING |
| 122 | #define CONFIG_CMD_USB |
| 123 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 124 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 125 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | # define CONFIG_SYS_LOWBOOT 1 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 127 | #endif |
| 128 | |
| 129 | /* |
| 130 | * Autobooting |
| 131 | */ |
| 132 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 133 | |
wdenk | 7dd1329 | 2004-07-11 20:04:51 +0000 | [diff] [blame] | 134 | #define CONFIG_PREBOOT \ |
| 135 | "setenv stdout serial;setenv stderr serial;" \ |
| 136 | "echo;" \ |
Wolfgang Denk | 1baed66 | 2008-03-03 12:16:44 +0100 | [diff] [blame] | 137 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 138 | "echo" |
| 139 | |
| 140 | #undef CONFIG_BOOTARGS |
| 141 | |
| 142 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 143 | "netdev=eth0\0" \ |
| 144 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 145 | "nfsroot=${serverip}:${rootpath}\0" \ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 146 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 147 | "addip=setenv bootargs ${bootargs} " \ |
| 148 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 149 | ":${hostname}:${netdev}:off panic=1\0" \ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 150 | "flash_nfs=run nfsargs addip;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 151 | "bootm ${kernel_addr}\0" \ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 152 | "flash_self=run ramargs addip;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 153 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 154 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 155 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
| 156 | "bootfile=/tftpboot/MPC5200/uImage\0" \ |
| 157 | "" |
| 158 | |
| 159 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 160 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 161 | /* |
| 162 | * IPB Bus clocking configuration. |
| 163 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 165 | |
| 166 | /* |
| 167 | * I2C configuration |
| 168 | */ |
| 169 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 171 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
| 173 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 174 | |
| 175 | /* |
| 176 | * EEPROM configuration |
| 177 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
| 179 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 180 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 181 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 182 | |
| 183 | /* |
| 184 | * Flash configuration |
| 185 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 187 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 188 | #if CONFIG_TOTAL5200_REV==2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | # define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ |
| 190 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START } |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 191 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
| 193 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 194 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 196 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 197 | |
| 198 | #if CONFIG_TOTAL5200_REV==1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | # define CONFIG_SYS_FLASH_BASE 0xFE000000 |
| 200 | # define CONFIG_SYS_FLASH_SIZE 0x02000000 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 201 | #elif CONFIG_TOTAL5200_REV==2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | # define CONFIG_SYS_FLASH_BASE 0xFA000000 |
| 203 | # define CONFIG_SYS_FLASH_SIZE 0x06000000 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 204 | #endif /* CONFIG_TOTAL5200_REV */ |
| 205 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #if defined(CONFIG_SYS_LOWBOOT) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 207 | # define CONFIG_ENV_ADDR 0xFE040000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 208 | #else /* CONFIG_SYS_LOWBOOT */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 209 | # define CONFIG_ENV_ADDR 0xFFF40000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 210 | #endif /* CONFIG_SYS_LOWBOOT */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 211 | |
| 212 | /* |
| 213 | * Environment settings |
| 214 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 215 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 216 | #define CONFIG_ENV_SIZE 0x40000 |
| 217 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 218 | #define CONFIG_ENV_OVERWRITE 1 |
| 219 | |
| 220 | /* |
| 221 | * Memory map |
| 222 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 224 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
| 225 | #define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */ |
| 226 | #define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */ |
| 227 | #define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */ |
| 228 | #define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 229 | |
| 230 | /* Use SRAM until RAM will be available */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 232 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 233 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 236 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 238 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 239 | # define CONFIG_SYS_RAMBOOT 1 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 240 | #endif |
| 241 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 242 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 243 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 244 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 245 | |
| 246 | /* |
| 247 | * Ethernet configuration |
| 248 | */ |
| 249 | #define CONFIG_MPC5xxx_FEC 1 |
Ben Warren | bc1b917 | 2009-02-05 23:58:25 -0800 | [diff] [blame] | 250 | #define CONFIG_MPC5xxx_FEC_SEVENWIRE |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 251 | /* dummy, 7-wire FEC does not have phy address */ |
| 252 | #define CONFIG_PHY_ADDR 0x00 |
| 253 | |
| 254 | /* |
| 255 | * GPIO configuration |
| 256 | * |
| 257 | * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 |
| 258 | * Reserved 0 |
| 259 | * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 |
| 260 | * CS7: Interrupt GPIO on PSC3_5 0 |
| 261 | * CS8: Interrupt GPIO on PSC3_4 0 |
| 262 | * ATA: reset default, changed in ATA driver 00 |
| 263 | * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 |
| 264 | * IRDA: reset default, changed in IrDA driver 000 |
| 265 | * ETHER: reset default, changed in Ethernet driver 0000 |
| 266 | * PCI_DIS: reset default, changed in PCI driver 0 |
| 267 | * USB_SE: reset default, changed in USB driver 0 |
| 268 | * USB: reset default, changed in USB driver 00 |
| 269 | * PSC3: SPI and UART functionality without CD 1100 |
| 270 | * Reserved 0 |
| 271 | * PSC2: CAN1/2 001 |
| 272 | * Reserved 0 |
| 273 | * PSC1: reset default, changed in AC'97 driver 000 |
| 274 | * |
| 275 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 276 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 277 | |
| 278 | /* |
| 279 | * Miscellaneous configurable options |
| 280 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Jon Loeliger | 59cf509 | 2007-07-04 22:31:15 -0500 | [diff] [blame] | 282 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 283 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 284 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 286 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 287 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 288 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 289 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 290 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 291 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
| 292 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 293 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 294 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 295 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 296 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
Jon Loeliger | 59cf509 | 2007-07-04 22:31:15 -0500 | [diff] [blame] | 297 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 298 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
Jon Loeliger | 59cf509 | 2007-07-04 22:31:15 -0500 | [diff] [blame] | 299 | #endif |
| 300 | |
| 301 | |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 302 | /* |
| 303 | * Various low-level settings |
| 304 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 305 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
| 306 | #define CONFIG_SYS_HID0_FINAL HID0_ICE |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 307 | |
| 308 | #if CONFIG_TOTAL5200_REV==1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 309 | # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
| 310 | # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ |
| 311 | # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
| 312 | # define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
| 313 | # define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 314 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | # define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE) |
| 316 | # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ |
| 317 | # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
| 318 | # define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE) |
| 319 | # define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */ |
| 320 | # define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
| 321 | # define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE |
| 322 | # define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */ |
| 323 | # define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 324 | #endif |
| 325 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 326 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE |
| 327 | #define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */ |
| 328 | #define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 329 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 330 | #define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE |
| 331 | #define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */ |
| 332 | #define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 333 | |
| 334 | #if CONFIG_TOTAL5200_REV==1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 335 | # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
| 336 | # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ |
| 337 | # define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 338 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 339 | # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
| 340 | # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ |
| 341 | # define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 342 | #endif |
| 343 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 344 | #define CONFIG_SYS_CS_BURST 0x00000000 |
| 345 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 346 | |
| 347 | /*----------------------------------------------------------------------- |
| 348 | * USB stuff |
| 349 | *----------------------------------------------------------------------- |
| 350 | */ |
| 351 | #define CONFIG_USB_CLOCK 0x0001BBBB |
| 352 | #define CONFIG_USB_CONFIG 0x00001000 |
| 353 | |
| 354 | /*----------------------------------------------------------------------- |
| 355 | * IDE/ATA stuff Supports IDE harddisk |
| 356 | *----------------------------------------------------------------------- |
| 357 | */ |
| 358 | |
| 359 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
| 360 | |
| 361 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 362 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
| 363 | |
| 364 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
| 365 | #define CONFIG_IDE_PREINIT |
| 366 | |
Grzegorz Bernacki | 81e8199 | 2009-03-17 10:06:39 +0100 | [diff] [blame] | 367 | #define CONFIG_SYS_ATA_CS_ON_I2C2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 368 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 369 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 370 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 371 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 372 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 373 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 374 | |
| 375 | /* Offset for data I/O */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 376 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 377 | |
| 378 | /* Offset for normal register accesses */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 379 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 380 | |
| 381 | /* Offset for alternate registers */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 382 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 383 | |
| 384 | /* Interval between registers */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 385 | #define CONFIG_SYS_ATA_STRIDE 4 |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 386 | |
| 387 | #endif /* __CONFIG_H */ |