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wdenkcc3f8a92004-07-11 19:17:20 +00001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenkcc3f8a92004-07-11 19:17:20 +00009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * Check valid setting of revision define.
16 * Total5100 and Total5200 Rev.1 are identical except for the processor.
17 */
18#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
19#error CONFIG_TOTAL5200_REV must be 1 or 2
20#endif
21
22/*
23 * High Level Configuration Options
24 * (easy to change)
25 */
26
27#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
Detlev Zundela414c7a2010-03-12 10:01:12 +010028#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
wdenkcc3f8a92004-07-11 19:17:20 +000029#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
30
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020031/*
32 * Valid values for CONFIG_SYS_TEXT_BASE are:
33 * 0xFFF00000 boot high (standard configuration)
34 * 0xFE000000 boot low
35 * 0x00100000 boot from RAM (for testing only)
36 */
37#ifndef CONFIG_SYS_TEXT_BASE
38#define CONFIG_SYS_TEXT_BASE 0xFFF00000
39#endif
40
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenkcc3f8a92004-07-11 19:17:20 +000042
Becky Bruce03ea1be2008-05-08 19:02:12 -050043#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
wdenkcc3f8a92004-07-11 19:17:20 +000045/*
46 * Serial console configuration
47 */
48#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkcc3f8a92004-07-11 19:17:20 +000051
wdenk7dd13292004-07-11 20:04:51 +000052/*
53 * Video console
54 */
wdenk7ac16102004-08-01 22:48:16 +000055#define CONFIG_VIDEO
wdenk7dd13292004-07-11 20:04:51 +000056#define CONFIG_VIDEO_SED13806
57#define CONFIG_VIDEO_SED13806_16BPP
58
59#define CONFIG_CFB_CONSOLE
60#define CONFIG_VIDEO_LOGO
61/* #define CONFIG_VIDEO_BMP_LOGO */
62#define CONFIG_CONSOLE_EXTRA_INFO
63#define CONFIG_VGA_AS_SINGLE_DEVICE
64#define CONFIG_VIDEO_SW_CURSOR
65#define CONFIG_SPLASH_SCREEN
66
wdenkcc3f8a92004-07-11 19:17:20 +000067
wdenkcc3f8a92004-07-11 19:17:20 +000068/*
69 * PCI Mapping:
70 * 0x40000000 - 0x4fffffff - PCI Memory
71 * 0x50000000 - 0x50ffffff - PCI IO Space
72 */
73#define CONFIG_PCI 1
74#define CONFIG_PCI_PNP 1
75#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liew521f97b2008-03-30 01:19:06 -050076#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenkcc3f8a92004-07-11 19:17:20 +000077
78#define CONFIG_PCI_MEM_BUS 0x40000000
79#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
80#define CONFIG_PCI_MEM_SIZE 0x10000000
81
82#define CONFIG_PCI_IO_BUS 0x50000000
83#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
84#define CONFIG_PCI_IO_SIZE 0x01000000
85
Marian Balakowiczaab8c492005-10-28 22:30:33 +020086#define CONFIG_MII 1
wdenkcc3f8a92004-07-11 19:17:20 +000087#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkcc3f8a92004-07-11 19:17:20 +000089#define CONFIG_NS8382X 1
90
wdenkcc3f8a92004-07-11 19:17:20 +000091/* Partitions */
92#define CONFIG_MAC_PARTITION
93#define CONFIG_DOS_PARTITION
94
95/* USB */
wdenkcc3f8a92004-07-11 19:17:20 +000096#define CONFIG_USB_OHCI
wdenkcc3f8a92004-07-11 19:17:20 +000097#define CONFIG_USB_STORAGE
Jon Loeliger59cf5092007-07-04 22:31:15 -050098
wdenkcc3f8a92004-07-11 19:17:20 +000099
100/*
Jon Loeligerbeb9ff42007-07-10 09:22:23 -0500101 * BOOTP options
102 */
103#define CONFIG_BOOTP_BOOTFILESIZE
104#define CONFIG_BOOTP_BOOTPATH
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107
108
109/*
Jon Loeliger59cf5092007-07-04 22:31:15 -0500110 * Command line configuration.
wdenkcc3f8a92004-07-11 19:17:20 +0000111 */
Jon Loeliger59cf5092007-07-04 22:31:15 -0500112#include <config_cmd_default.h>
113
Detlev Zundela414c7a2010-03-12 10:01:12 +0100114#define CONFIG_CMD_PCI
wdenkcc3f8a92004-07-11 19:17:20 +0000115
Jon Loeliger59cf5092007-07-04 22:31:15 -0500116#define CONFIG_CMD_BMP
117#define CONFIG_CMD_EEPROM
118#define CONFIG_CMD_FAT
119#define CONFIG_CMD_I2C
120#define CONFIG_CMD_IDE
121#define CONFIG_CMD_PING
122#define CONFIG_CMD_USB
123
wdenkcc3f8a92004-07-11 19:17:20 +0000124
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200125#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126# define CONFIG_SYS_LOWBOOT 1
wdenkcc3f8a92004-07-11 19:17:20 +0000127#endif
128
129/*
130 * Autobooting
131 */
132#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
133
wdenk7dd13292004-07-11 20:04:51 +0000134#define CONFIG_PREBOOT \
135 "setenv stdout serial;setenv stderr serial;" \
136 "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +0100137 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkcc3f8a92004-07-11 19:17:20 +0000138 "echo"
139
140#undef CONFIG_BOOTARGS
141
142#define CONFIG_EXTRA_ENV_SETTINGS \
143 "netdev=eth0\0" \
144 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100145 "nfsroot=${serverip}:${rootpath}\0" \
wdenkcc3f8a92004-07-11 19:17:20 +0000146 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100147 "addip=setenv bootargs ${bootargs} " \
148 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
149 ":${hostname}:${netdev}:off panic=1\0" \
wdenkcc3f8a92004-07-11 19:17:20 +0000150 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100151 "bootm ${kernel_addr}\0" \
wdenkcc3f8a92004-07-11 19:17:20 +0000152 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100153 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
154 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkcc3f8a92004-07-11 19:17:20 +0000155 "rootpath=/opt/eldk/ppc_82xx\0" \
156 "bootfile=/tftpboot/MPC5200/uImage\0" \
157 ""
158
159#define CONFIG_BOOTCOMMAND "run flash_self"
160
wdenkcc3f8a92004-07-11 19:17:20 +0000161/*
162 * IPB Bus clocking configuration.
163 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkcc3f8a92004-07-11 19:17:20 +0000165
166/*
167 * I2C configuration
168 */
169#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
wdenkcc3f8a92004-07-11 19:17:20 +0000171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
173#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkcc3f8a92004-07-11 19:17:20 +0000174
175/*
176 * EEPROM configuration
177 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
179#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
180#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
181#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenkcc3f8a92004-07-11 19:17:20 +0000182
183/*
184 * Flash configuration
185 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200187#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenkcc3f8a92004-07-11 19:17:20 +0000188#if CONFIG_TOTAL5200_REV==2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
190# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
wdenkcc3f8a92004-07-11 19:17:20 +0000191#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
193# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
wdenkcc3f8a92004-07-11 19:17:20 +0000194#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_EMPTY_INFO
196#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenkcc3f8a92004-07-11 19:17:20 +0000197
198#if CONFIG_TOTAL5200_REV==1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199# define CONFIG_SYS_FLASH_BASE 0xFE000000
200# define CONFIG_SYS_FLASH_SIZE 0x02000000
wdenkcc3f8a92004-07-11 19:17:20 +0000201#elif CONFIG_TOTAL5200_REV==2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202# define CONFIG_SYS_FLASH_BASE 0xFA000000
203# define CONFIG_SYS_FLASH_SIZE 0x06000000
wdenkcc3f8a92004-07-11 19:17:20 +0000204#endif /* CONFIG_TOTAL5200_REV */
205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#if defined(CONFIG_SYS_LOWBOOT)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200207# define CONFIG_ENV_ADDR 0xFE040000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#else /* CONFIG_SYS_LOWBOOT */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200209# define CONFIG_ENV_ADDR 0xFFF40000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#endif /* CONFIG_SYS_LOWBOOT */
wdenkcc3f8a92004-07-11 19:17:20 +0000211
212/*
213 * Environment settings
214 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200215#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200216#define CONFIG_ENV_SIZE 0x40000
217#define CONFIG_ENV_SECT_SIZE 0x40000
wdenkcc3f8a92004-07-11 19:17:20 +0000218#define CONFIG_ENV_OVERWRITE 1
219
220/*
221 * Memory map
222 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_SDRAM_BASE 0x00000000
224#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
225#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */
226#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */
227#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */
228#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */
wdenkcc3f8a92004-07-11 19:17:20 +0000229
230/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200232#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
wdenkcc3f8a92004-07-11 19:17:20 +0000233
Wolfgang Denk0191e472010-10-26 14:34:52 +0200234#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkcc3f8a92004-07-11 19:17:20 +0000236
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200237#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
239# define CONFIG_SYS_RAMBOOT 1
wdenkcc3f8a92004-07-11 19:17:20 +0000240#endif
241
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
243#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
244#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkcc3f8a92004-07-11 19:17:20 +0000245
246/*
247 * Ethernet configuration
248 */
249#define CONFIG_MPC5xxx_FEC 1
Ben Warrenbc1b9172009-02-05 23:58:25 -0800250#define CONFIG_MPC5xxx_FEC_SEVENWIRE
wdenkcc3f8a92004-07-11 19:17:20 +0000251/* dummy, 7-wire FEC does not have phy address */
252#define CONFIG_PHY_ADDR 0x00
253
254/*
255 * GPIO configuration
256 *
257 * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
258 * Reserved 0
259 * ALTs: CAN1/2 on PSC2, SPI on PSC3 00
260 * CS7: Interrupt GPIO on PSC3_5 0
261 * CS8: Interrupt GPIO on PSC3_4 0
262 * ATA: reset default, changed in ATA driver 00
263 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
264 * IRDA: reset default, changed in IrDA driver 000
265 * ETHER: reset default, changed in Ethernet driver 0000
266 * PCI_DIS: reset default, changed in PCI driver 0
267 * USB_SE: reset default, changed in USB driver 0
268 * USB: reset default, changed in USB driver 00
269 * PSC3: SPI and UART functionality without CD 1100
270 * Reserved 0
271 * PSC2: CAN1/2 001
272 * Reserved 0
273 * PSC1: reset default, changed in AC'97 driver 000
274 *
275 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10
wdenkcc3f8a92004-07-11 19:17:20 +0000277
278/*
279 * Miscellaneous configurable options
280 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200281#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger59cf5092007-07-04 22:31:15 -0500282#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkcc3f8a92004-07-11 19:17:20 +0000284#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkcc3f8a92004-07-11 19:17:20 +0000286#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200287#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
288#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
289#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkcc3f8a92004-07-11 19:17:20 +0000290
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200291#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
292#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenkcc3f8a92004-07-11 19:17:20 +0000293
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkcc3f8a92004-07-11 19:17:20 +0000295
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger59cf5092007-07-04 22:31:15 -0500297#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200298# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger59cf5092007-07-04 22:31:15 -0500299#endif
300
301
wdenkcc3f8a92004-07-11 19:17:20 +0000302/*
303 * Various low-level settings
304 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
306#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenkcc3f8a92004-07-11 19:17:20 +0000307
308#if CONFIG_TOTAL5200_REV==1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
310# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
311# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
312# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
313# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */
wdenkcc3f8a92004-07-11 19:17:20 +0000314#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200315# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
316# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
317# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
318# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
319# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */
320# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
321# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
322# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */
323# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
wdenkcc3f8a92004-07-11 19:17:20 +0000324#endif
325
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200326#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE
327#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */
328#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
wdenkcc3f8a92004-07-11 19:17:20 +0000329
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE
331#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */
332#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
wdenkcc3f8a92004-07-11 19:17:20 +0000333
334#if CONFIG_TOTAL5200_REV==1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200335# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
336# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
337# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
wdenkcc3f8a92004-07-11 19:17:20 +0000338#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200339# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
340# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
341# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
wdenkcc3f8a92004-07-11 19:17:20 +0000342#endif
343
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200344#define CONFIG_SYS_CS_BURST 0x00000000
345#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenkcc3f8a92004-07-11 19:17:20 +0000346
347/*-----------------------------------------------------------------------
348 * USB stuff
349 *-----------------------------------------------------------------------
350 */
351#define CONFIG_USB_CLOCK 0x0001BBBB
352#define CONFIG_USB_CONFIG 0x00001000
353
354/*-----------------------------------------------------------------------
355 * IDE/ATA stuff Supports IDE harddisk
356 *-----------------------------------------------------------------------
357 */
358
359#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
360
361#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
362#undef CONFIG_IDE_LED /* LED for ide not supported */
363
364#define CONFIG_IDE_RESET /* reset for ide supported */
365#define CONFIG_IDE_PREINIT
366
Grzegorz Bernacki81e81992009-03-17 10:06:39 +0100367#define CONFIG_SYS_ATA_CS_ON_I2C2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
369#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkcc3f8a92004-07-11 19:17:20 +0000370
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200371#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkcc3f8a92004-07-11 19:17:20 +0000372
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200373#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenkcc3f8a92004-07-11 19:17:20 +0000374
375/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200376#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenkcc3f8a92004-07-11 19:17:20 +0000377
378/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200379#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenkcc3f8a92004-07-11 19:17:20 +0000380
381/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200382#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
wdenkcc3f8a92004-07-11 19:17:20 +0000383
384/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200385#define CONFIG_SYS_ATA_STRIDE 4
wdenkcc3f8a92004-07-11 19:17:20 +0000386
387#endif /* __CONFIG_H */