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wdenk7d393ae2002-10-25 21:08:05 +00001/*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk7d393ae2002-10-25 21:08:05 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
20#define CONFIG_4xx 1 /* ...member of PPC4xx family */
21#define CONFIG_MIP405 1 /* ...on a MIP405 board */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020022
23#define CONFIG_SYS_TEXT_BASE 0xFFF80000
24
wdenk7d393ae2002-10-25 21:08:05 +000025/***********************************************************
wdenke39c2842003-06-04 15:05:30 +000026 * Note that it may also be a MIP405T board which is a subset of the
27 * MIP405
28 ***********************************************************/
29/***********************************************************
30 * WARNING:
31 * CONFIG_BOOT_PCI is only used for first boot-up and should
32 * NOT be enabled for production bootloader
33 ***********************************************************/
wdenk57b2d802003-06-27 21:31:46 +000034/*#define CONFIG_BOOT_PCI 1*/
wdenke39c2842003-06-04 15:05:30 +000035/***********************************************************
wdenk7d393ae2002-10-25 21:08:05 +000036 * Clock
37 ***********************************************************/
38#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
39
wdenk7d393ae2002-10-25 21:08:05 +000040
Jon Loeliger446e1f52007-07-08 14:14:17 -050041/*
Jon Loeligered26c742007-07-10 09:10:49 -050042 * BOOTP options
43 */
44#define CONFIG_BOOTP_BOOTFILESIZE
45#define CONFIG_BOOTP_BOOTPATH
46#define CONFIG_BOOTP_GATEWAY
47#define CONFIG_BOOTP_HOSTNAME
48
49
50/*
Jon Loeliger446e1f52007-07-08 14:14:17 -050051 * Command line configuration.
52 */
53#include <config_cmd_default.h>
wdenke39c2842003-06-04 15:05:30 +000054
Jon Loeliger446e1f52007-07-08 14:14:17 -050055#define CONFIG_CMD_CACHE
56#define CONFIG_CMD_DATE
57#define CONFIG_CMD_DHCP
58#define CONFIG_CMD_EEPROM
59#define CONFIG_CMD_ELF
60#define CONFIG_CMD_FAT
61#define CONFIG_CMD_I2C
62#define CONFIG_CMD_IDE
63#define CONFIG_CMD_IRQ
64#define CONFIG_CMD_JFFS2
65#define CONFIG_CMD_MII
66#define CONFIG_CMD_PCI
67#define CONFIG_CMD_PING
68#define CONFIG_CMD_REGINFO
69#define CONFIG_CMD_SAVES
70#define CONFIG_CMD_BSP
71
72#if !defined(CONFIG_MIP405T)
73 #define CONFIG_CMD_USB
wdenke39c2842003-06-04 15:05:30 +000074#endif
75
wdenk7d393ae2002-10-25 21:08:05 +000076
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_HUSH_PARSER
wdenk7d393ae2002-10-25 21:08:05 +000078/**************************************************************
79 * I2C Stuff:
80 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
81 * 0x53.
82 * The Atmel EEPROM uses 16Bit addressing.
83 ***************************************************************/
84
Dirk Eibach42b204f2013-04-25 02:40:01 +000085#define CONFIG_SYS_I2C
86#define CONFIG_SYS_I2C_PPC4XX
87#define CONFIG_SYS_I2C_PPC4XX_CH0
88#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
89#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenk7d393ae2002-10-25 21:08:05 +000090
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
92#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
wdenk7d393ae2002-10-25 21:08:05 +000093/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
95#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenk7d393ae2002-10-25 21:08:05 +000096 /* 64 byte page write mode using*/
97 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk7d393ae2002-10-25 21:08:05 +000099
100
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200101#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200102#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
103#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
wdenk7d393ae2002-10-25 21:08:05 +0000104
105/***************************************************************
106 * Definitions for Serial Presence Detect EEPROM address
107 * (to get SDRAM settings)
108 ***************************************************************/
wdenke39c2842003-06-04 15:05:30 +0000109/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
Wolfgang Denka1be4762008-05-20 16:00:29 +0200110#define SDRAM_EEPROM_READ_ADDRESS 0xA1
wdenke39c2842003-06-04 15:05:30 +0000111*/
wdenk7d393ae2002-10-25 21:08:05 +0000112/**************************************************************
113 * Environment definitions
114 **************************************************************/
115#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
116#define CONFIG_BOOTDELAY 5
117/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk7b4e3472005-08-13 02:04:37 +0200118/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200119#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenk7d393ae2002-10-25 21:08:05 +0000120
wdenkb02744a2003-04-05 00:53:31 +0000121#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenk7d393ae2002-10-25 21:08:05 +0000122#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
123
124#define CONFIG_IPADDR 10.0.0.100
125#define CONFIG_SERVERIP 10.0.0.1
126#define CONFIG_PREBOOT
127/***************************************************************
128 * defines if the console is stored in the environment
129 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenk7d393ae2002-10-25 21:08:05 +0000131/***************************************************************
132 * defines if an overwrite_console function exists
133 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
135#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenk7d393ae2002-10-25 21:08:05 +0000136/***************************************************************
137 * defines if the overwrite_console should be stored in the
138 * environment
139 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenk7d393ae2002-10-25 21:08:05 +0000141
142/**************************************************************
143 * loads config
144 *************************************************************/
145#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7d393ae2002-10-25 21:08:05 +0000147
148#define CONFIG_MISC_INIT_R
149/***********************************************************
150 * Miscellaneous configurable options
151 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger446e1f52007-07-08 14:14:17 -0500153#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000155#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000157#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
159#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
160#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7d393ae2002-10-25 21:08:05 +0000161
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
163#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenk7d393ae2002-10-25 21:08:05 +0000164
Stefan Roese3ddce572010-09-20 16:05:31 +0200165#define CONFIG_CONS_INDEX 1 /* Use UART0 */
166#define CONFIG_SYS_NS16550
167#define CONFIG_SYS_NS16550_SERIAL
168#define CONFIG_SYS_NS16550_REG_SIZE 1
169#define CONFIG_SYS_NS16550_CLK get_serial_clock()
170
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
172#define CONFIG_SYS_BASE_BAUD 916667
wdenk7d393ae2002-10-25 21:08:05 +0000173
174/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7d393ae2002-10-25 21:08:05 +0000176 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
177 57600, 115200, 230400, 460800, 921600 }
178
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
180#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk7d393ae2002-10-25 21:08:05 +0000181
wdenk7d393ae2002-10-25 21:08:05 +0000182/*-----------------------------------------------------------------------
183 * PCI stuff
184 *-----------------------------------------------------------------------
185 */
186#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
187#define PCI_HOST_FORCE 1 /* configure as pci host */
188#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
189
190#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000191#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenk7d393ae2002-10-25 21:08:05 +0000192#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
193#define CONFIG_PCI_PNP /* pci plug-and-play */
194 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
196#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
197#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
198#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
199#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
200#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
201#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
202#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenk7d393ae2002-10-25 21:08:05 +0000203
204/*-----------------------------------------------------------------------
205 * Start addresses for the final memory configuration
206 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7d393ae2002-10-25 21:08:05 +0000208 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_SDRAM_BASE 0x00000000
210#define CONFIG_SYS_FLASH_BASE 0xFFF80000
211#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
212#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
213#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenk7d393ae2002-10-25 21:08:05 +0000214
215/*
216 * For booting Linux, the board info and command line data
217 * have to be in the first 8 MB of memory, since this is
218 * the maximum mapped by the Linux kernel during initialization.
219 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7d393ae2002-10-25 21:08:05 +0000221/*-----------------------------------------------------------------------
222 * FLASH organization
223 */
David Müllera24c8782011-12-22 13:38:21 +0100224#define CONFIG_SYS_UPDATE_FLASH_SIZE
225#define CONFIG_SYS_FLASH_PROTECTION
226#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk7d393ae2002-10-25 21:08:05 +0000227
David Müllera24c8782011-12-22 13:38:21 +0100228#define CONFIG_SYS_FLASH_CFI
229#define CONFIG_FLASH_CFI_DRIVER
230
231#define CONFIG_FLASH_SHOW_PROGRESS 45
232
233#define CONFIG_SYS_MAX_FLASH_BANKS 1
234#define CONFIG_SYS_MAX_FLASH_SECT 256
wdenk7d393ae2002-10-25 21:08:05 +0000235
Wolfgang Denk47f57792005-08-08 01:03:24 +0200236/*
237 * JFFS2 partitions
238 *
239 */
240/* No command line, one static partition, whole device */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100241#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200242#define CONFIG_JFFS2_DEV "nor0"
243#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
244#define CONFIG_JFFS2_PART_OFFSET 0x00000000
245
246/* mtdparts command line support */
247/* Note: fake mtd_id used, no linux mtd map file */
248/*
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100249#define CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200250#define MTDIDS_DEFAULT "nor0=mip405-0"
251#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
252*/
wdenke97d3d92004-02-23 22:22:28 +0000253
wdenk7d393ae2002-10-25 21:08:05 +0000254/*-----------------------------------------------------------------------
wdenke97d3d92004-02-23 22:22:28 +0000255 * Logbuffer Configuration
256 */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200257#undef CONFIG_LOGBUFFER /* supported but not enabled */
wdenke97d3d92004-02-23 22:22:28 +0000258/*-----------------------------------------------------------------------
259 * Bootcountlimit Configuration
260 */
261#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
262
263/*-----------------------------------------------------------------------
264 * POST Configuration
265 */
266#if 0 /* enable this if POST is desired (is supported but not enabled) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
268 CONFIG_SYS_POST_CPU | \
269 CONFIG_SYS_POST_RTC | \
270 CONFIG_SYS_POST_I2C)
wdenke97d3d92004-02-23 22:22:28 +0000271
272#endif
wdenk7d393ae2002-10-25 21:08:05 +0000273/*
274 * Init Memory Controller:
275 */
wdenk2c9b05d2003-09-10 22:30:53 +0000276#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
277#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
278/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
279#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenk7d393ae2002-10-25 21:08:05 +0000280
wdenkda55c6e2004-01-20 23:12:12 +0000281#define CONFIG_BOARD_EARLY_INIT_F 1
David Müllera24c8782011-12-22 13:38:21 +0100282#define CONFIG_BOARD_EARLY_INIT_R
wdenk7d393ae2002-10-25 21:08:05 +0000283
284/* Peripheral Bus Mapping */
285#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
286#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
287#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
288
289#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
Wolfgang Denka1be4762008-05-20 16:00:29 +0200290#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
wdenk7d393ae2002-10-25 21:08:05 +0000291
292
wdenk7d393ae2002-10-25 21:08:05 +0000293/*-----------------------------------------------------------------------
294 * Definitions for initial stack pointer and data area (in On Chip SRAM)
295 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_TEMP_STACK_OCM 1
297#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
298#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
299#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200300#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200301#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenke97d3d92004-02-23 22:22:28 +0000302/* reserve some memory for POST and BOOT limit info */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
wdenke97d3d92004-02-23 22:22:28 +0000304
wdenke97d3d92004-02-23 22:22:28 +0000305#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200306#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
wdenke97d3d92004-02-23 22:22:28 +0000307#endif
wdenk7d393ae2002-10-25 21:08:05 +0000308
wdenk7d393ae2002-10-25 21:08:05 +0000309/***********************************************************************
310 * External peripheral base address
311 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenk7d393ae2002-10-25 21:08:05 +0000313
314/***********************************************************************
315 * Last Stage Init
316 ***********************************************************************/
317#define CONFIG_LAST_STAGE_INIT
318/************************************************************
319 * Ethernet Stuff
320 ***********************************************************/
Ben Warren3a918a62008-10-27 23:50:15 -0700321#define CONFIG_PPC4xx_EMAC
wdenk7d393ae2002-10-25 21:08:05 +0000322#define CONFIG_MII 1 /* MII PHY management */
323#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenke97d3d92004-02-23 22:22:28 +0000324#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
325#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
wdenk7d393ae2002-10-25 21:08:05 +0000326/************************************************************
327 * RTC
328 ***********************************************************/
329#define CONFIG_RTC_MC146818
330#undef CONFIG_WATCHDOG /* watchdog disabled */
331
332/************************************************************
333 * IDE/ATA stuff
334 ************************************************************/
wdenke39c2842003-06-04 15:05:30 +0000335#if defined(CONFIG_MIP405T)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200336#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
wdenke39c2842003-06-04 15:05:30 +0000337#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200338#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
wdenke39c2842003-06-04 15:05:30 +0000339#endif
340
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenk7d393ae2002-10-25 21:08:05 +0000342
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
344#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
345#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
346#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
347#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
348#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenk7d393ae2002-10-25 21:08:05 +0000349
350#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
351#undef CONFIG_IDE_LED /* no led for ide supported */
352#define CONFIG_IDE_RESET /* reset for ide supported... */
353#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk2c9b05d2003-09-10 22:30:53 +0000354#define CONFIG_SUPPORT_VFAT
wdenk7d393ae2002-10-25 21:08:05 +0000355/************************************************************
356 * ATAPI support (experimental)
357 ************************************************************/
358#define CONFIG_ATAPI /* enable ATAPI Support */
359
360/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000361 * DISK Partition support
362 ************************************************************/
363#define CONFIG_DOS_PARTITION
364#define CONFIG_MAC_PARTITION
365#define CONFIG_ISO_PARTITION /* Experimental */
366
367/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000368 * Keyboard support
369 ************************************************************/
370#undef CONFIG_ISA_KEYBOARD
371
372/************************************************************
373 * Video support
374 ************************************************************/
375#define CONFIG_VIDEO /*To enable video controller support */
376#define CONFIG_VIDEO_CT69000
377#define CONFIG_CFB_CONSOLE
378#define CONFIG_VIDEO_LOGO
379#define CONFIG_CONSOLE_EXTRA_INFO
380#define CONFIG_VGA_AS_SINGLE_DEVICE
381#define CONFIG_VIDEO_SW_CURSOR
382#undef CONFIG_VIDEO_ONBOARD
383/************************************************************
384 * USB support EXPERIMENTAL
385 ************************************************************/
wdenke39c2842003-06-04 15:05:30 +0000386#if !defined(CONFIG_MIP405T)
wdenk7d393ae2002-10-25 21:08:05 +0000387#define CONFIG_USB_UHCI
388#define CONFIG_USB_KEYBOARD
389#define CONFIG_USB_STORAGE
390
391/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD2a7a0312009-05-16 12:14:54 +0200392#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenke39c2842003-06-04 15:05:30 +0000393#endif
wdenk7d393ae2002-10-25 21:08:05 +0000394/************************************************************
395 * Debug support
396 ************************************************************/
Jon Loeliger446e1f52007-07-08 14:14:17 -0500397#if defined(CONFIG_CMD_KGDB)
wdenk7d393ae2002-10-25 21:08:05 +0000398#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk7d393ae2002-10-25 21:08:05 +0000399#endif
400
401/************************************************************
wdenk4ea537d2003-12-07 18:32:37 +0000402 * support BZIP2 compression
403 ************************************************************/
404#define CONFIG_BZIP2 1
405
406/************************************************************
wdenk7d393ae2002-10-25 21:08:05 +0000407 * Ident
408 ************************************************************/
wdenke39c2842003-06-04 15:05:30 +0000409
wdenk7d393ae2002-10-25 21:08:05 +0000410#define VERSION_TAG "released"
wdenke39c2842003-06-04 15:05:30 +0000411#if !defined(CONFIG_MIP405T)
412#define CONFIG_ISO_STRING "MEV-10072-001"
413#else
414#define CONFIG_ISO_STRING "MEV-10082-001"
415#endif
416
417#if !defined(CONFIG_BOOT_PCI)
418#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
419#else
420#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
421#endif
wdenk7d393ae2002-10-25 21:08:05 +0000422
423
424#endif /* __CONFIG_H */