blob: 39eb2ef1336bd8600f4c3628ad0aa3d88097f132 [file] [log] [blame]
Stefan Roese5ff4c3f2005-08-15 12:31:23 +02001/*
2 * (C) Copyright 2004 Sandburst Corporation
3 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese5ff4c3f2005-08-15 12:31:23 +02005 */
6
7/************************************************************************
8 * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
Wolfgang Denk85faa8b2005-08-15 16:03:56 +02009 * design.
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020010 ***********************************************************************/
11
12/*
13 * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
14 *
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20/*-----------------------------------------------------------------------
21 * High Level Configuration Options
22 *----------------------------------------------------------------------*/
Wolfgang Denk85faa8b2005-08-15 16:03:56 +020023#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
24#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +020025#define CONFIG_440 1 /* ... PPC440 family */
Wolfgang Denk85faa8b2005-08-15 16:03:56 +020026#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020027#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Wolfgang Denk85faa8b2005-08-15 16:03:56 +020028#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
29#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020030
31#define CONFIG_SYS_TEXT_BASE 0xFFF80000
32
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
Wolfgang Denk85faa8b2005-08-15 16:03:56 +020034#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020035
36#define CONFIG_VERY_BIG_RAM 1
37#define CONFIG_VERSION_VARIABLE
38
39#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
40
41/*-----------------------------------------------------------------------
42 * Base addresses -- Note these are effective addresses where the
43 * actual resources get mapped (not physical addresses)
44 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
46#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
47#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
48#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
50#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020051
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
53#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
54#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
55#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
56#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020057
58/* Here for completeness */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020059#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020060
61/*-----------------------------------------------------------------------
62 * Initial RAM & stack pointer (placed in internal SRAM)
63 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_TEMP_STACK_OCM 1
65#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
66#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020067#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020068
Wolfgang Denk0191e472010-10-26 14:34:52 +020069#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidmanf969a682010-09-20 08:51:53 +020070#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020071
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
73#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020074
75/*-----------------------------------------------------------------------
76 * Serial Port
77 *----------------------------------------------------------------------*/
Stefan Roese3ddce572010-09-20 16:05:31 +020078#define CONFIG_CONS_INDEX 1 /* Use UART0 */
79#define CONFIG_SYS_NS16550
80#define CONFIG_SYS_NS16550_SERIAL
81#define CONFIG_SYS_NS16550_REG_SIZE 1
82#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020083#define CONFIG_BAUDRATE 9600
84
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020086 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
87
88/*-----------------------------------------------------------------------
89 * NVRAM/RTC
90 *
91 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
92 * The DS1743 code assumes this condition (i.e. -- it assumes the base
93 * address for the RTC registers is:
94 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
Stefan Roese5ff4c3f2005-08-15 12:31:23 +020096 *
97 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
Wolfgang Denk85faa8b2005-08-15 16:03:56 +020099#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200100
101/*-----------------------------------------------------------------------
102 * FLASH related
103 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
105#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200106
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#undef CONFIG_SYS_FLASH_CHECKSUM
108#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
109#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200110
111/*-----------------------------------------------------------------------
112 * DDR SDRAM
113 *----------------------------------------------------------------------*/
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200114#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
115#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200116
117/*-----------------------------------------------------------------------
118 * I2C
119 *----------------------------------------------------------------------*/
Dirk Eibach42b204f2013-04-25 02:40:01 +0000120#define CONFIG_SYS_I2C
121#define CONFIG_SYS_I2C_PPC4XX
122#define CONFIG_SYS_I2C_PPC4XX_CH0
123#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
124#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
125#define CONFIG_SYS_I2C_PPC4XX_CH1
126#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
127#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
128#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200129
130/*-----------------------------------------------------------------------
131 * Environment
132 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200133#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200134#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200135#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200136#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200137
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200138#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200140
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200141#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200142
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200143#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200145
146/*-----------------------------------------------------------------------
147 * Networking
148 *----------------------------------------------------------------------*/
Ben Warren3a918a62008-10-27 23:50:15 -0700149#define CONFIG_PPC4xx_EMAC
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200150#define CONFIG_MII 1 /* MII PHY management */
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200151#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
152#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
153#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
154#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200155#define CONFIG_HAS_ETH0
156#define CONFIG_HAS_ETH1
157#define CONFIG_HAS_ETH2
158#define CONFIG_HAS_ETH3
Stefan Roese0c7ffc02005-08-16 18:18:00 +0200159#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200160#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
161#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
162#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200163#define CONFIG_PHY_RESET_DELAY 1000
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200164#define CONFIG_NETMASK 255.255.0.0
165#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
166#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200168
169
Jon Loeligerb1840de2007-07-08 13:46:18 -0500170/*
Jon Loeligered26c742007-07-10 09:10:49 -0500171 * BOOTP options
172 */
173#define CONFIG_BOOTP_BOOTFILESIZE
174#define CONFIG_BOOTP_BOOTPATH
175#define CONFIG_BOOTP_GATEWAY
176#define CONFIG_BOOTP_HOSTNAME
177
178
179/*
Jon Loeligerb1840de2007-07-08 13:46:18 -0500180 * Command line configuration.
181 */
182#include <config_cmd_default.h>
183
184#define CONFIG_CMD_PCI
185#define CONFIG_CMD_IRQ
186#define CONFIG_CMD_I2C
187#define CONFIG_CMD_DHCP
188#define CONFIG_CMD_DATE
189#define CONFIG_CMD_BEDBUG
190#define CONFIG_CMD_PING
191#define CONFIG_CMD_DIAG
192#define CONFIG_CMD_MII
193#define CONFIG_CMD_NET
194#define CONFIG_CMD_ELF
195#define CONFIG_CMD_IDE
196#define CONFIG_CMD_FAT
197
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200198
199/* Include NetConsole support */
200#define CONFIG_NETCONSOLE
201
202/* Include auto complete with tabs */
203#define CONFIG_AUTO_COMPLETE 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_LONGHELP /* undef to save memory */
207#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200208
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200210
211
212/*-----------------------------------------------------------------------
213 * Console Buffer
214 *----------------------------------------------------------------------*/
Jon Loeligerb1840de2007-07-08 13:46:18 -0500215#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200217#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200219#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200221 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
223#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200224
225/*-----------------------------------------------------------------------
226 * Memory Test
227 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
229#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200230
231/*-----------------------------------------------------------------------
232 * Compact Flash (in true IDE mode)
233 *----------------------------------------------------------------------*/
234#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
235#undef CONFIG_IDE_LED /* no led for ide supported */
236
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200237#define CONFIG_IDE_RESET /* reset for ide supported */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
239#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200240
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
242#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
243#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
244#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
245#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200246
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200248 to get to the correct offset */
249#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200250
251/*-----------------------------------------------------------------------
252 * PCI
253 *----------------------------------------------------------------------*/
254/* General PCI */
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200255#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000256#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200257#define CONFIG_PCI_PNP /* do pci plug-and-play */
258#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200260
261/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200263
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
265#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200266
267/*
268 * For booting Linux, the board info and command line data
269 * have to be in the first 8 MB of memory, since this is
270 * the maximum mapped by the Linux kernel during initialization.
271 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200273
Jon Loeligerb1840de2007-07-08 13:46:18 -0500274#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200275#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200276#endif
277
278/*-----------------------------------------------------------------------
279 * Miscellaneous configurable options
280 *----------------------------------------------------------------------*/
Wolfgang Denk85faa8b2005-08-15 16:03:56 +0200281#undef CONFIG_WATCHDOG /* watchdog disabled */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
283#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200284
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200285#endif /* __CONFIG_H */