wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 Picture Elements, Inc. |
| 3 | * Stephen Williams <steve@icarus.com> |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | /* |
| 16 | * High Level Configuration Options for the JSE board |
| 17 | * (Theoretically easy to change, but the board is fixed.) |
| 18 | */ |
| 19 | |
| 20 | #define CONFIG_JSE 1 |
| 21 | /* JSE has a PPC405GPr */ |
| 22 | #define CONFIG_405GP 1 |
| 23 | /* ... which is a 4xxx series */ |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 24 | #define CONFIG_4x 1 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 25 | /* ... with a 33MHz OSC. connected to the SysCLK input */ |
| 26 | #define CONFIG_SYS_CLK_FREQ 33333333 |
| 27 | /* ... with on-chip memory here (4KBytes) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 28 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000 |
| 29 | #define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 30 | /* Do not set up locked dcache as init ram. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 31 | #undef CONFIG_SYS_INIT_DCACHE_CS |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 32 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 33 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
| 34 | |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 35 | /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ |
| 36 | #define CONFIG_SYSTEMACE 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 37 | #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000 |
| 38 | #define CONFIG_SYS_SYSTEMACE_WIDTH 8 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 39 | #define CONFIG_DOS_PARTITION 1 |
| 40 | |
| 41 | /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 42 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 43 | /* ... place INIT RAM in the OCM address */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | # define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 45 | /* ... give it the whole init ram */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 46 | # define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 47 | /* ... Shave a bit off the end for global data */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 48 | # define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 49 | /* ... and place the stack pointer at the top of what's left. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 50 | # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 51 | |
| 52 | /* Enable board_pre_init function */ |
| 53 | #define CONFIG_BOARD_PRE_INIT 1 |
| 54 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
| 55 | /* Disable post-clk setup init function */ |
| 56 | #undef CONFIG_BOARD_POSTCLK_INIT |
| 57 | /* Disable call to post_init_f: late init function. */ |
| 58 | #undef CONFIG_POST |
| 59 | /* Enable DRAM test. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 60 | #define CONFIG_SYS_DRAM_TEST 1 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 61 | /* Enable misc_init_r function. */ |
| 62 | #define CONFIG_MISC_INIT_R 1 |
| 63 | |
| 64 | /* JSE has EEPROM chips that are good for environment. */ |
Jean-Christophe PLAGNIOL-VILLARD | fdb79c3 | 2008-09-10 22:47:59 +0200 | [diff] [blame] | 65 | #undef CONFIG_ENV_IS_IN_NVRAM |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 66 | #undef CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 67 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
Jean-Christophe PLAGNIOL-VILLARD | 68a8756 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 68 | #undef CONFIG_ENV_IS_NOWHERE |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 69 | |
| 70 | /* This is the 7bit address of the device, not including P. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 72 | /* After the device address, need one more address byte. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 74 | /* The EEPROM is 512 bytes. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_EEPROM_SIZE 512 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 76 | /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 77 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
| 78 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 79 | /* Put the environment in the second half. */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 80 | #define CONFIG_ENV_OFFSET 0x00 |
| 81 | #define CONFIG_ENV_SIZE 512 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 82 | |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 83 | /* The JSE connects UART1 to the console tap connector. */ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 84 | #define CONFIG_CONS_INDEX 2 |
| 85 | #define CONFIG_SYS_NS16550 |
| 86 | #define CONFIG_SYS_NS16550_SERIAL |
| 87 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 88 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 89 | |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 90 | /* Set console baudrate to 9600 */ |
| 91 | #define CONFIG_BAUDRATE 9600 |
| 92 | |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 93 | /* |
| 94 | * Configuration related to auto-boot. |
| 95 | * |
| 96 | * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait |
| 97 | * before resorting to autoboot. This value can be overridden by the |
| 98 | * bootdelay environment variable. |
| 99 | * |
| 100 | * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the |
| 101 | * user that an autoboot will happen. |
| 102 | * |
| 103 | * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will |
| 104 | * execute to boot the JSE. This loads the uimage and initrd.img files |
| 105 | * from CompactFlash into memory, then boots them from memory. |
| 106 | * |
| 107 | * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get |
| 108 | * it going on the JSE. |
| 109 | */ |
| 110 | #define CONFIG_BOOTDELAY 5 |
| 111 | #define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw" |
| 112 | #define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000" |
| 113 | |
| 114 | |
| 115 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 117 | |
Ben Warren | 3a918a6 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 118 | #define CONFIG_PPC4xx_EMAC |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 119 | #define CONFIG_MII 1 /* MII PHY management */ |
| 120 | #define CONFIG_PHY_ADDR 1 /* PHY address */ |
| 121 | |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 122 | |
Jon Loeliger | b1840de | 2007-07-08 13:46:18 -0500 | [diff] [blame] | 123 | /* |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 124 | * BOOTP options |
| 125 | */ |
| 126 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 127 | #define CONFIG_BOOTP_BOOTPATH |
| 128 | #define CONFIG_BOOTP_GATEWAY |
| 129 | #define CONFIG_BOOTP_HOSTNAME |
| 130 | |
| 131 | |
| 132 | /* |
Jon Loeliger | b1840de | 2007-07-08 13:46:18 -0500 | [diff] [blame] | 133 | * Command line configuration. |
| 134 | */ |
| 135 | #include <config_cmd_default.h> |
| 136 | |
| 137 | #define CONFIG_CMD_DHCP |
| 138 | #define CONFIG_CMD_EEPROM |
| 139 | #define CONFIG_CMD_ELF |
| 140 | #define CONFIG_CMD_FAT |
| 141 | #define CONFIG_CMD_FLASH |
| 142 | #define CONFIG_CMD_IRQ |
| 143 | #define CONFIG_CMD_MII |
| 144 | #define CONFIG_CMD_NET |
| 145 | #define CONFIG_CMD_PCI |
| 146 | #define CONFIG_CMD_PING |
| 147 | |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 148 | |
| 149 | /* watchdog disabled */ |
| 150 | #undef CONFIG_WATCHDOG |
| 151 | /* SPD EEPROM (sdram speed config) disabled */ |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 152 | #undef CONFIG_SPD_EEPROM |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 153 | #undef SPD_EEPROM_ADDRESS |
| 154 | |
| 155 | /* |
| 156 | * Miscellaneous configurable options |
| 157 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 159 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 161 | |
Jon Loeliger | b1840de | 2007-07-08 13:46:18 -0500 | [diff] [blame] | 162 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 163 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 164 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 166 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 168 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 169 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 170 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 172 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 173 | |
| 174 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
| 176 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. |
| 177 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 178 | * The Linux BASE_BAUD define should match this configuration. |
| 179 | * baseBaud = cpuClock/(uartDivisor*16) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 181 | * set Linux BASE_BAUD to 403200. |
| 182 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
| 184 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
| 185 | #define CONFIG_SYS_BASE_BAUD 691200 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 186 | |
| 187 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 188 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 189 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
| 190 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 191 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 192 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 193 | |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 194 | #define CONFIG_SYS_I2C |
| 195 | #define CONFIG_SYS_I2C_PPC4XX |
| 196 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| 197 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
| 198 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 199 | |
| 200 | |
| 201 | /*----------------------------------------------------------------------- |
| 202 | * PCI stuff |
| 203 | *----------------------------------------------------------------------- |
| 204 | */ |
| 205 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
| 206 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 207 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
| 208 | |
| 209 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 210 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 211 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
| 212 | #undef CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 213 | /* resource configuration */ |
| 214 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 215 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
| 216 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ |
| 217 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| 218 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
| 219 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 220 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ |
| 221 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ |
| 222 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 223 | |
| 224 | /*----------------------------------------------------------------------- |
| 225 | * External peripheral base address |
| 226 | *----------------------------------------------------------------------- |
| 227 | */ |
| 228 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| 229 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ |
| 230 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
| 232 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 |
| 233 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 234 | |
| 235 | /*----------------------------------------------------------------------- |
| 236 | * Start addresses for the final memory configuration |
| 237 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 238 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 239 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 240 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 241 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 |
| 242 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 243 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
| 244 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 245 | |
| 246 | /* |
| 247 | * For booting Linux, the board info and command line data |
| 248 | * have to be in the first 8 MB of memory, since this is |
| 249 | * the maximum mapped by the Linux kernel during initialization. |
| 250 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 252 | |
| 253 | /*----------------------------------------------------------------------- |
| 254 | * FLASH organization |
| 255 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 256 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 257 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 258 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 260 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 261 | |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 262 | /* |
| 263 | * Init Memory Controller: |
| 264 | * |
| 265 | * BR0/1 and OR0/1 (FLASH) |
| 266 | */ |
| 267 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 268 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 269 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
| 270 | |
| 271 | |
| 272 | /* Configuration Port location */ |
| 273 | #define CONFIG_PORT_ADDR 0xF0000500 |
| 274 | |
Jon Loeliger | b1840de | 2007-07-08 13:46:18 -0500 | [diff] [blame] | 275 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 276 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
wdenk | 634d2f7 | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 277 | #endif |
| 278 | #endif /* __CONFIG_H */ |