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wdenk76dd6c72004-06-09 14:47:54 +00001/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Interphase iSPAN Communications Controllers
6 * (453x and others). Tested on 4532.
7 *
8 * Derived from iSPAN 4539 port (iphase4539) by
9 * Wolfgang Grandegger <wg@denx.de>
10 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenk76dd6c72004-06-09 14:47:54 +000012 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
17#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050018#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk76dd6c72004-06-09 14:47:54 +000019
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
21
wdenk76dd6c72004-06-09 14:47:54 +000022/*-----------------------------------------------------------------------
23 * Select serial console configuration
24 *
25 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
26 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
27 * for SCC).
28 *
29 * If CONFIG_CONS_NONE is defined, then the serial console routines must be
30 * defined elsewhere (for example, on the cogent platform, there are serial
31 * ports on the motherboard which are used for the serial console - see
32 * cogent/cma101/serial.[ch]).
33 */
34#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
35#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
36#undef CONFIG_CONS_NONE /* Define if console on something else */
37#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
38
39/*-----------------------------------------------------------------------
40 * Select Ethernet configuration
41 *
42 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
43 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
44 * for FCC).
45 *
46 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
Jon Loeliger2517d972007-07-09 17:15:49 -050047 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk76dd6c72004-06-09 14:47:54 +000048 */
49#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
50#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
51#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
52#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
53
54#ifdef CONFIG_ETHER_ON_FCC
55
56#if CONFIG_ETHER_INDEX == 3
57
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_PHY_ADDR 0
Mike Frysinger109de972011-10-17 05:38:58 +000059#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
60#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
wdenk76dd6c72004-06-09 14:47:54 +000061
62#endif /* CONFIG_ETHER_INDEX == 3 */
63
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_CPMFCR_RAMTYPE 0
65#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenk76dd6c72004-06-09 14:47:54 +000066
67#define CONFIG_MII /* MII PHY management */
68#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
69/*
70 * GPIO pins used for bit-banged MII communications
71 */
72#define MDIO_PORT 3 /* Port D */
Luigi 'Comio' Mantellini25e30722009-10-10 12:42:22 +020073#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
74 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
75#define MDC_DECLARE MDIO_DECLARE
76
wdenk76dd6c72004-06-09 14:47:54 +000077
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020078#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
79#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
wdenk76dd6c72004-06-09 14:47:54 +000080
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
82#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
83#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
wdenk76dd6c72004-06-09 14:47:54 +000084
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
86 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
wdenk76dd6c72004-06-09 14:47:54 +000087
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
89 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
wdenk76dd6c72004-06-09 14:47:54 +000090
91#define MIIDELAY udelay(1)
92
93#endif /* CONFIG_ETHER_ON_FCC */
94
95#define CONFIG_8260_CLKIN 65536000 /* in Hz */
96#define CONFIG_BAUDRATE 38400
97
Jon Loeligerb1840de2007-07-08 13:46:18 -050098
99/*
Jon Loeligerf5709d12007-07-10 09:02:57 -0500100 * BOOTP options
101 */
102#define CONFIG_BOOTP_BOOTFILESIZE
103#define CONFIG_BOOTP_BOOTPATH
104#define CONFIG_BOOTP_GATEWAY
105#define CONFIG_BOOTP_HOSTNAME
106
107
108/*
Jon Loeligerb1840de2007-07-08 13:46:18 -0500109 * Command line configuration.
110 */
111#include <config_cmd_default.h>
112
113#define CONFIG_CMD_ASKENV
114#define CONFIG_CMD_DHCP
115#define CONFIG_CMD_IMMAP
116#define CONFIG_CMD_MII
117#define CONFIG_CMD_PING
118#define CONFIG_CMD_REGINFO
wdenk76dd6c72004-06-09 14:47:54 +0000119
wdenk76dd6c72004-06-09 14:47:54 +0000120
121#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
122#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
123#define CONFIG_BOOTARGS "root=/dev/ram rw"
124
125#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
126#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
127
128/*-----------------------------------------------------------------------
129 * Miscellaneous configurable options
130 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_LONGHELP /* #undef to save memory */
133#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
135#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk76dd6c72004-06-09 14:47:54 +0000137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
wdenk76dd6c72004-06-09 14:47:54 +0000140
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
wdenk76dd6c72004-06-09 14:47:54 +0000142
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_RESET_ADDRESS 0x09900000
wdenk76dd6c72004-06-09 14:47:54 +0000144
145#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
146
147/*-----------------------------------------------------------------------
148 * For booting Linux, the board info and command line data
149 * have to be in the first 8 MB of memory, since this is
150 * the maximum mapped by the Linux kernel during initialization.
151 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk76dd6c72004-06-09 14:47:54 +0000153
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200154#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk76dd6c72004-06-09 14:47:54 +0000156#ifdef CONFIG_BZIP2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
wdenk76dd6c72004-06-09 14:47:54 +0000158#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
wdenk76dd6c72004-06-09 14:47:54 +0000160#endif /* CONFIG_BZIP2 */
161
162/*-----------------------------------------------------------------------
163 * FLASH organization
164 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_BASE 0xFE000000
166#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200167#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
169#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
wdenk76dd6c72004-06-09 14:47:54 +0000170
171/* Environment is in flash, there is little space left in Serial EEPROM */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200172#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200173#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
174#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200176#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
177#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk76dd6c72004-06-09 14:47:54 +0000178
179/*-----------------------------------------------------------------------
180 * Hard Reset Configuration Words
181 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182 * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk76dd6c72004-06-09 14:47:54 +0000183 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk76dd6c72004-06-09 14:47:54 +0000185 */
186/* 0x1686B245 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
wdenk76dd6c72004-06-09 14:47:54 +0000188 HRCW_L2CPC10 | HRCW_ISB110 |\
189 HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
190 HRCW_CS10PC01 | HRCW_MODCK_H0101 \
191 )
192/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_HRCW_SLAVE1 0
194#define CONFIG_SYS_HRCW_SLAVE2 0
195#define CONFIG_SYS_HRCW_SLAVE3 0
196#define CONFIG_SYS_HRCW_SLAVE4 0
197#define CONFIG_SYS_HRCW_SLAVE5 0
198#define CONFIG_SYS_HRCW_SLAVE6 0
199#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk76dd6c72004-06-09 14:47:54 +0000200
201/*-----------------------------------------------------------------------
202 * Internal Memory Mapped Register
203 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_IMMR 0xF0F00000
205#ifdef CONFIG_SYS_REV_B
206#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
207#endif /* CONFIG_SYS_REV_B */
wdenk76dd6c72004-06-09 14:47:54 +0000208/*-----------------------------------------------------------------------
209 * Definitions for initial stack pointer and data area (in DPRAM)
210 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200212#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200213#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk76dd6c72004-06-09 14:47:54 +0000215
216/*-----------------------------------------------------------------------
wdenk76dd6c72004-06-09 14:47:54 +0000217 * Cache Configuration
218 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenk76dd6c72004-06-09 14:47:54 +0000220
221/*-----------------------------------------------------------------------
222 * HIDx - Hardware Implementation-dependent Registers 2-11
223 *-----------------------------------------------------------------------
224 * HID0 also contains cache control.
225 *
226 * HID1 has only read-only information - nothing to set.
227 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk76dd6c72004-06-09 14:47:54 +0000229 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
231#define CONFIG_SYS_HID2 0
wdenk76dd6c72004-06-09 14:47:54 +0000232
233/*-----------------------------------------------------------------------
234 * RMR - Reset Mode Register 5-5
235 *-----------------------------------------------------------------------
236 * turn on Checkstop Reset Enable
237 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_RMR RMR_CSRE
wdenk76dd6c72004-06-09 14:47:54 +0000239
240/*-----------------------------------------------------------------------
241 * BCR - Bus Configuration 4-25
242 *-----------------------------------------------------------------------
243 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200244#define CONFIG_SYS_BCR 0xA01C0000
wdenk76dd6c72004-06-09 14:47:54 +0000245
246/*-----------------------------------------------------------------------
247 * SIUMCR - SIU Module Configuration 4-31
248 *-----------------------------------------------------------------------
249 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200250#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
wdenk76dd6c72004-06-09 14:47:54 +0000251
252/*-----------------------------------------------------------------------
253 * SYPCR - System Protection Control 4-35
254 * SYPCR can only be written once after reset!
255 *-----------------------------------------------------------------------
256 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
257 */
258#if defined (CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk76dd6c72004-06-09 14:47:54 +0000260 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
261#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk76dd6c72004-06-09 14:47:54 +0000263 SYPCR_SWRI|SYPCR_SWP)
264#endif /* CONFIG_WATCHDOG */
265
266/*-----------------------------------------------------------------------
267 * TMCNTSC - Time Counter Status and Control 4-40
268 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
269 * and enable Time Counter
270 *-----------------------------------------------------------------------
271 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk76dd6c72004-06-09 14:47:54 +0000273
274/*-----------------------------------------------------------------------
275 * PISCR - Periodic Interrupt Status and Control 4-42
276 *-----------------------------------------------------------------------
277 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
278 * Periodic timer
279 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200280#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk76dd6c72004-06-09 14:47:54 +0000281
282/*-----------------------------------------------------------------------
283 * SCCR - System Clock Control 9-8
284 *-----------------------------------------------------------------------
285 * Ensure DFBRG is Divide by 16
286 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200287#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenk76dd6c72004-06-09 14:47:54 +0000288
289/*-----------------------------------------------------------------------
290 * RCCR - RISC Controller Configuration 13-7
291 *-----------------------------------------------------------------------
292 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200293#define CONFIG_SYS_RCCR 0
wdenk76dd6c72004-06-09 14:47:54 +0000294
295/*-----------------------------------------------------------------------
296 * Init Memory Controller:
297 *
298 * Bank Bus Machine PortSize Device
299 * ---- --- ------- ----------------------------- ------
300 * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
301 * 1 60x SDRAM 64 bit SDRAM
302 * 2 Local SDRAM 32 bit SDRAM
303 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200304#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
wdenk76dd6c72004-06-09 14:47:54 +0000305 controller, rely on initialisation
306 performed by the Interphase boot firmware.
307 */
308
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_OR0_PRELIM 0xFE000882
310#ifdef CONFIG_SYS_REV_B
311#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
wdenk76dd6c72004-06-09 14:47:54 +0000312#else /* Rev. D */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200313#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
314#endif /* CONFIG_SYS_REV_B */
wdenk76dd6c72004-06-09 14:47:54 +0000315
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200316#define CONFIG_SYS_MPTPR 0x7F00
wdenk76dd6c72004-06-09 14:47:54 +0000317
318/* Please note that 60x SDRAM MUST start at 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200319#define CONFIG_SYS_SDRAM_BASE 0x00000000
320#define CONFIG_SYS_60x_BR 0x00000041
321#define CONFIG_SYS_60x_OR 0xF0002CD0
322#define CONFIG_SYS_PSDMR 0x0049929A
323#define CONFIG_SYS_PSRT 0x07
wdenk76dd6c72004-06-09 14:47:54 +0000324
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325#define CONFIG_SYS_LSDRAM_BASE 0xF7000000
326#define CONFIG_SYS_LOC_BR 0x00001861
327#define CONFIG_SYS_LOC_OR 0xFF803280
328#define CONFIG_SYS_LSDMR 0x8285A552
329#define CONFIG_SYS_LSRT 0x07
wdenk76dd6c72004-06-09 14:47:54 +0000330
331#endif /* __CONFIG_H */