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stroesea9484a92004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
stroesea9484a92004-12-16 18:05:42 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
21#define CONFIG_4xx 1 /* ...member of PPC4xx family */
22#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
23#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
24
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26
stroesea9484a92004-12-16 18:05:42 +000027#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser5c506212009-09-16 22:03:07 -050028#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroesea9484a92004-12-16 18:05:42 +000029
30#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
31
32#define CONFIG_BAUDRATE 9600
33#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
34
35#undef CONFIG_BOOTARGS
36#undef CONFIG_BOOTCOMMAND
37
38#define CONFIG_PREBOOT /* enable preboot variable */
39
40#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea9484a92004-12-16 18:05:42 +000042
Ben Warren3a918a62008-10-27 23:50:15 -070043#define CONFIG_PPC4xx_EMAC
stroesea9484a92004-12-16 18:05:42 +000044#define CONFIG_MII 1 /* MII PHY management */
45#define CONFIG_PHY_ADDR 0 /* PHY address */
46#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs196088b2007-06-24 17:41:21 +020047#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
48
Matthias Fuchs196088b2007-06-24 17:41:21 +020049#undef CONFIG_HAS_ETH1
stroesea9484a92004-12-16 18:05:42 +000050
51#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
52
Jon Loeliger1cb2cb62007-07-09 21:16:53 -050053/*
54 * BOOTP options
55 */
56#define CONFIG_BOOTP_SUBNETMASK
57#define CONFIG_BOOTP_GATEWAY
58#define CONFIG_BOOTP_HOSTNAME
59#define CONFIG_BOOTP_BOOTPATH
60#define CONFIG_BOOTP_DNS
61#define CONFIG_BOOTP_DNS2
62#define CONFIG_BOOTP_SEND_HOSTNAME
63
stroesea9484a92004-12-16 18:05:42 +000064
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050065/*
66 * Command line configuration.
67 */
68#include <config_cmd_default.h>
stroesea9484a92004-12-16 18:05:42 +000069
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050070#define CONFIG_CMD_DHCP
71#define CONFIG_CMD_PCI
72#define CONFIG_CMD_IRQ
73#define CONFIG_CMD_IDE
74#define CONFIG_CMD_FAT
75#define CONFIG_CMD_ELF
76#define CONFIG_CMD_DATE
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050077#define CONFIG_CMD_I2C
78#define CONFIG_CMD_MII
79#define CONFIG_CMD_PING
80#define CONFIG_CMD_BSP
81#define CONFIG_CMD_EEPROM
82
stroesea9484a92004-12-16 18:05:42 +000083#define CONFIG_MAC_PARTITION
84#define CONFIG_DOS_PARTITION
85
86#define CONFIG_SUPPORT_VFAT
87
88#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
89
stroesea9484a92004-12-16 18:05:42 +000090#undef CONFIG_WATCHDOG /* watchdog disabled */
91
92#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
93
94/*
95 * Miscellaneous configurable options
96 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_LONGHELP /* undef to save memory */
stroesea9484a92004-12-16 18:05:42 +000098
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
stroesea9484a92004-12-16 18:05:42 +0000100
Jon Loeliger8c5f4a42007-07-05 19:52:35 -0500101#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea9484a92004-12-16 18:05:42 +0000103#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea9484a92004-12-16 18:05:42 +0000105#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea9484a92004-12-16 18:05:42 +0000109
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea9484a92004-12-16 18:05:42 +0000111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea9484a92004-12-16 18:05:42 +0000113
114#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
117#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea9484a92004-12-16 18:05:42 +0000118
Stefan Roese3ddce572010-09-20 16:05:31 +0200119#define CONFIG_CONS_INDEX 1 /* Use UART0 */
120#define CONFIG_SYS_NS16550
121#define CONFIG_SYS_NS16550_SERIAL
122#define CONFIG_SYS_NS16550_REG_SIZE 1
123#define CONFIG_SYS_NS16550_CLK get_serial_clock()
124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_BASE_BAUD 691200
stroesea9484a92004-12-16 18:05:42 +0000127
128/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea9484a92004-12-16 18:05:42 +0000130 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
131 57600, 115200, 230400, 460800, 921600 }
132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
134#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea9484a92004-12-16 18:05:42 +0000135
stroesea9484a92004-12-16 18:05:42 +0000136#define CONFIG_LOOPW 1 /* enable loopw command */
137
138#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
139
140/* Only interrupt boot if special string is typed */
Stefan Roese37628252008-08-06 14:05:38 +0200141#define CONFIG_AUTOBOOT_KEYED 1
142#define CONFIG_AUTOBOOT_PROMPT \
143 "Autobooting in %d seconds\n", bootdelay
stroesea9484a92004-12-16 18:05:42 +0000144#undef CONFIG_AUTOBOOT_DELAY_STR
145#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */
146#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
147
148#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
149
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea9484a92004-12-16 18:05:42 +0000151
152/*-----------------------------------------------------------------------
153 * PCI stuff
154 *-----------------------------------------------------------------------
155 */
156#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
157#define PCI_HOST_FORCE 1 /* configure as pci host */
158#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
159
160#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000161#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea9484a92004-12-16 18:05:42 +0000162#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
163#define CONFIG_PCI_PNP /* do pci plug-and-play */
164 /* resource configuration */
165
166#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
167
168#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
169
170#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
173#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
174#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
175#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
176#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
177#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
178#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
179#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
180#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
Matthias Fuchse717a502012-11-02 14:30:34 +0100181#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
stroesea9484a92004-12-16 18:05:42 +0000182
Matthias Fuchsa9d47992009-09-07 17:00:41 +0200183#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
184
stroesea9484a92004-12-16 18:05:42 +0000185/*-----------------------------------------------------------------------
186 * IDE/ATA stuff
187 *-----------------------------------------------------------------------
188 */
189#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
190#undef CONFIG_IDE_LED /* no led for ide supported */
191#define CONFIG_IDE_RESET 1 /* reset for ide supported */
192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
194#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
stroesea9484a92004-12-16 18:05:42 +0000195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
197#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroesea9484a92004-12-16 18:05:42 +0000198
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
200#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
201#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea9484a92004-12-16 18:05:42 +0000202
203/*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea9484a92004-12-16 18:05:42 +0000207 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_SDRAM_BASE 0x00000000
209#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
210#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
211#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
212#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
stroesea9484a92004-12-16 18:05:42 +0000213
214/*
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
218 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea9484a92004-12-16 18:05:42 +0000220/*-----------------------------------------------------------------------
221 * FLASH organization
222 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
224#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea9484a92004-12-16 18:05:42 +0000225
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
227#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
stroesea9484a92004-12-16 18:05:42 +0000228
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
230#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
231#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea9484a92004-12-16 18:05:42 +0000232/*
233 * The following defines are added for buggy IOP480 byte interface.
234 * All other boards should use the standard values (CPCI405 etc.)
235 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
237#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
238#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea9484a92004-12-16 18:05:42 +0000239
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea9484a92004-12-16 18:05:42 +0000241
stroesea9484a92004-12-16 18:05:42 +0000242#if 0 /* Use NVRAM for environment variables */
243/*-----------------------------------------------------------------------
244 * NVRAM organization
245 */
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200246#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200247#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
248#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
stroesea9484a92004-12-16 18:05:42 +0000250
251#else /* Use EEPROM for environment variables */
252
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200253#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200254#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
255#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
stroesea9484a92004-12-16 18:05:42 +0000256 /* total size of a CAT24WC16 is 2048 bytes */
257#endif
258
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
260#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
261#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
stroesea9484a92004-12-16 18:05:42 +0000262
263/*-----------------------------------------------------------------------
264 * I2C EEPROM (CAT24WC16) for environment
265 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000266#define CONFIG_SYS_I2C
267#define CONFIG_SYS_I2C_PPC4XX
268#define CONFIG_SYS_I2C_PPC4XX_CH0
269#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
270#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
stroesea9484a92004-12-16 18:05:42 +0000271
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
273#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea9484a92004-12-16 18:05:42 +0000274/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200275#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
276#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea9484a92004-12-16 18:05:42 +0000277 /* 16 byte page write mode using*/
278 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea9484a92004-12-16 18:05:42 +0000280
stroesea9484a92004-12-16 18:05:42 +0000281/*
282 * Init Memory Controller:
283 *
284 * BR0/1 and OR0/1 (FLASH)
285 */
286
287#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
288#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
289
290/*-----------------------------------------------------------------------
291 * External Bus Controller (EBC) Setup
292 */
293
294/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_SYS_EBC_PB0AP 0x92015480
296#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea9484a92004-12-16 18:05:42 +0000297
298/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_EBC_PB1AP 0x92015480
300#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
stroesea9484a92004-12-16 18:05:42 +0000301
302/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
304#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
305#define CONFIG_SYS_LED_ADDR 0xF0000380
stroesea9484a92004-12-16 18:05:42 +0000306
307/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200308#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
309#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea9484a92004-12-16 18:05:42 +0000310
311/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
313#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
314#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
stroesea9484a92004-12-16 18:05:42 +0000315
316/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
318#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
stroesea9484a92004-12-16 18:05:42 +0000319
320/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200321#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
322#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
323#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
stroesea9484a92004-12-16 18:05:42 +0000324
325/*-----------------------------------------------------------------------
326 * FPGA stuff
327 */
328/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200329#define CONFIG_SYS_FPGA_MODE 0x00
330#define CONFIG_SYS_FPGA_STATUS 0x02
331#define CONFIG_SYS_FPGA_TS 0x04
332#define CONFIG_SYS_FPGA_TS_LOW 0x06
333#define CONFIG_SYS_FPGA_TS_CAP0 0x10
334#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
335#define CONFIG_SYS_FPGA_TS_CAP1 0x14
336#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
337#define CONFIG_SYS_FPGA_TS_CAP2 0x18
338#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
339#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
340#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
stroesea9484a92004-12-16 18:05:42 +0000341
342/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
344#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
345#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
346#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
347#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
348#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
stroesea9484a92004-12-16 18:05:42 +0000349
350/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200351#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
352#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
353#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
354#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
355#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
stroesea9484a92004-12-16 18:05:42 +0000356
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200357#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
358#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
stroesea9484a92004-12-16 18:05:42 +0000359
360/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200361#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
362#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
363#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
364#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
365#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea9484a92004-12-16 18:05:42 +0000366
367/*-----------------------------------------------------------------------
368 * Definitions for initial stack pointer and data area (in data cache)
369 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200370#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
stroesea9484a92004-12-16 18:05:42 +0000371
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200372#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200373#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200374#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200375#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea9484a92004-12-16 18:05:42 +0000376
stroesea9484a92004-12-16 18:05:42 +0000377#endif /* __CONFIG_H */