blob: 4aed5afa3794072de25d215dc6247359829ff4b4 [file] [log] [blame]
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00005 */
6
7/*
8 * BSC9131 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#ifdef CONFIG_BSC9131RDB
15#define CONFIG_BSC9131
16#define CONFIG_NAND_FSL_IFC
17#endif
18
19#ifdef CONFIG_SPIFLASH
20#define CONFIG_RAMBOOT_SPIFLASH
21#define CONFIG_SYS_RAMBOOT
22#define CONFIG_SYS_EXTRA_ENV_RELOC
23#define CONFIG_SYS_TEXT_BASE 0x11000000
24#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
25#endif
26
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053027#ifdef CONFIG_NAND
28#define CONFIG_SPL
29#define CONFIG_SPL_INIT_MINIMAL
30#define CONFIG_SPL_SERIAL_SUPPORT
31#define CONFIG_SPL_NAND_SUPPORT
32#define CONFIG_SPL_NAND_MINIMAL
33#define CONFIG_SPL_FLUSH_IMAGE
34#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35
36#define CONFIG_SYS_TEXT_BASE 0x00201000
37#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
38#define CONFIG_SPL_MAX_SIZE 8192
39#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
40#define CONFIG_SPL_RELOC_STACK 0x00100000
41#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
42#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
43#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
44#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
45#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000046#endif
47
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053048#ifdef CONFIG_SPL_BUILD
49#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
50#else
51#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
52#endif
53
54
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000055/* High Level Configuration Options */
56#define CONFIG_BOOKE /* BOOKE */
57#define CONFIG_E500 /* BOOKE e500 family */
58#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
59#define CONFIG_FSL_IFC /* Enable IFC Support */
60
61#define CONFIG_FSL_LAW /* Use common FSL init code */
62#define CONFIG_TSEC_ENET
63#define CONFIG_ENV_OVERWRITE
64
65#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
Priyanka Jainf9146bd2013-04-01 12:12:45 +053066#if defined(CONFIG_SYS_CLK_100)
67#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
68#else
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000069#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
Priyanka Jainf9146bd2013-04-01 12:12:45 +053070#endif
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000071
72#define CONFIG_HWCONFIG
73/*
74 * These can be toggled for performance analysis, otherwise use default.
75 */
76#define CONFIG_L2_CACHE /* toggle L2 cache */
77#define CONFIG_BTB /* enable branch predition */
78
79#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
80#define CONFIG_SYS_MEMTEST_END 0x01ffffff
81
82/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -070083#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000084#undef CONFIG_SYS_DDR_RAW_TIMING
85#undef CONFIG_DDR_SPD
86#define CONFIG_SYS_SPD_BUS_NUM 0
87#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
88
89#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
90
91#ifndef __ASSEMBLY__
92extern unsigned long get_sdram_size(void);
93#endif
94#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
95#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97
98#define CONFIG_NUM_DDR_CONTROLLERS 1
99#define CONFIG_DIMM_SLOTS_PER_CTLR 1
100#define CONFIG_CHIP_SELECTS_PER_CTRL 1
101
102#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
103#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
104#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
105
106#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
107#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
108#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
109#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
110
111#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
112#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
113#define CONFIG_SYS_DDR_RCW_1 0x00000000
114#define CONFIG_SYS_DDR_RCW_2 0x00000000
115#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
116#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
117#define CONFIG_SYS_DDR_TIMING_4 0x00000001
118#define CONFIG_SYS_DDR_TIMING_5 0x02401400
119
120#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
121#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
122#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
123#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
124#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
125#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
126#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
127#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
128#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
129
130/*
131 * Base addresses -- Note these are effective addresses where the
132 * actual resources get mapped (not physical addresses)
133 */
134/* relocated CCSRBAR */
135#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
136#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
137
138#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
139 /* CONFIG_SYS_IMMR */
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530140/* DSP CCSRBAR */
141#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
142#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000143
144/*
145 * Memory map
146 *
147 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
148 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530149 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000150 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
151 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
152 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
153 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530154 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000155 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
156 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
157 *
158 */
159
160/*
161 * IFC Definitions
162 */
163#define CONFIG_SYS_NO_FLASH
164
165/* NAND Flash on IFC */
166#define CONFIG_SYS_NAND_BASE 0xff800000
167#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
168
169#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
170 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
171 | CSPR_MSEL_NAND /* MSEL = NAND */ \
172 | CSPR_V)
173#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
174
175#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
176 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
177 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
178 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
179 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
180 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
181 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
182
183/* NAND Flash Timing Params */
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530184#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
185 | FTIM0_NAND_TWP(0x05) \
186 | FTIM0_NAND_TWCHT(0x02) \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000187 | FTIM0_NAND_TWH(0x04))
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530188#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
189 | FTIM1_NAND_TWBE(0x1E) \
190 | FTIM1_NAND_TRR(0x07) \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000191 | FTIM1_NAND_TRP(0x05))
192#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
193 | FTIM2_NAND_TREH(0x04) \
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530194 | FTIM2_NAND_TWHRE(0x11))
195#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000196
197#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
198#define CONFIG_SYS_MAX_NAND_DEVICE 1
199#define CONFIG_MTD_NAND_VERIFY_WRITE
200#define CONFIG_CMD_NAND
201#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
202
203#define CONFIG_SYS_NAND_DDR_LAW 11
204
205/* Set up IFC registers for boot location NAND */
206#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
207#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
208#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
209#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
210#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
211#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
212#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
213
214#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
215
216#define CONFIG_SYS_INIT_RAM_LOCK
217#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
218#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */
219
220#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
221 - GENERATED_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
223
224#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
225#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
226
227/* Serial Port */
228#define CONFIG_CONS_INDEX 1
229#undef CONFIG_SERIAL_SOFTWARE_FIFO
230#define CONFIG_SYS_NS16550
231#define CONFIG_SYS_NS16550_SERIAL
232#define CONFIG_SYS_NS16550_REG_SIZE 1
233#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530234#ifdef CONFIG_SPL_BUILD
235#define CONFIG_NS16550_MIN_FUNCTIONS
236#endif
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000237
238#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
239
240#define CONFIG_SYS_BAUDRATE_TABLE \
241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
242
243#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
244
245/* Use the HUSH parser */
246#define CONFIG_SYS_HUSH_PARSER
247#ifdef CONFIG_SYS_HUSH_PARSER
248#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
249#endif
250
251/*
252 * Pass open firmware flat tree
253 */
254#define CONFIG_OF_LIBFDT
255#define CONFIG_OF_BOARD_SETUP
256#define CONFIG_OF_STDOUT_VIA_ALIAS
257
258/* new uImage format support */
259#define CONFIG_FIT
260#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
261
Heiko Schocherf2850742012-10-24 13:48:22 +0200262#define CONFIG_SYS_I2C
263#define CONFIG_SYS_I2C_FSL
264#define CONFIG_SYS_FSL_I2C_SPEED 400000
265#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
266#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000267
268/* I2C EEPROM */
269#define CONFIG_CMD_EEPROM
270#define CONFIG_SYS_I2C_MULTI_EEPROMS
271#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
272#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
273#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
274
275#define CONFIG_CMD_I2C
276
277
278#define CONFIG_FSL_ESPI
279/* eSPI - Enhanced SPI */
280#ifdef CONFIG_FSL_ESPI
281#define CONFIG_SPI_FLASH
282#define CONFIG_SPI_FLASH_SPANSION
283#define CONFIG_CMD_SF
284#define CONFIG_SF_DEFAULT_SPEED 10000000
285#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
286#endif
287
288#if defined(CONFIG_TSEC_ENET)
289
290#define CONFIG_MII /* MII PHY management */
291#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
292#define CONFIG_TSEC1 1
293#define CONFIG_TSEC1_NAME "eTSEC1"
294#define CONFIG_TSEC2 1
295#define CONFIG_TSEC2_NAME "eTSEC2"
296
297#define TSEC1_PHY_ADDR 0
298#define TSEC2_PHY_ADDR 3
299
300#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
301#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
302
303#define TSEC1_PHYIDX 0
304
305#define TSEC2_PHYIDX 0
306
307#define CONFIG_ETHPRIME "eTSEC1"
308
309#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
310
311#endif /* CONFIG_TSEC_ENET */
312
313/*
314 * Environment
315 */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000316#if defined(CONFIG_RAMBOOT_SPIFLASH)
317#define CONFIG_ENV_IS_IN_SPI_FLASH
318#define CONFIG_ENV_SPI_BUS 0
319#define CONFIG_ENV_SPI_CS 0
320#define CONFIG_ENV_SPI_MAX_HZ 10000000
321#define CONFIG_ENV_SPI_MODE 0
322#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
323#define CONFIG_ENV_SECT_SIZE 0x10000
324#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530325#elif defined(CONFIG_NAND)
326#define CONFIG_ENV_IS_IN_NAND
327#define CONFIG_SYS_EXTRA_ENV_RELOC
328#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
329#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
330#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
331#elif defined(CONFIG_SYS_RAMBOOT)
332#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000333#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530334#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000335#endif
336
337#define CONFIG_LOADS_ECHO /* echo on for serial download */
338#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
339
340/*
341 * Command line configuration.
342 */
343#include <config_cmd_default.h>
344
345#define CONFIG_CMD_DHCP
346#define CONFIG_CMD_ERRATA
347#define CONFIG_CMD_ELF
348#define CONFIG_CMD_EXT2
349#define CONFIG_CMD_FAT
350#define CONFIG_CMD_IRQ
351#define CONFIG_CMD_MII
352#define CONFIG_DOS_PARTITION
353#define CONFIG_CMD_PING
354#define CONFIG_CMD_REGINFO
355#define CONFIG_CMD_SETEXPR
356
357/*
358 * Miscellaneous configurable options
359 */
360#define CONFIG_SYS_LONGHELP /* undef to save memory */
361#define CONFIG_CMDLINE_EDITING /* Command-line editing */
362#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
363#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000364
365#if defined(CONFIG_CMD_KGDB)
366#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
367#else
368#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
369#endif
370#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
371 /* Print Buffer Size */
372#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
373#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000374
375/*
376 * For booting Linux, the board info and command line data
377 * have to be in the first 64 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization.
379 */
380#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
381#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
382
383#if defined(CONFIG_CMD_KGDB)
384#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000385#endif
386
387#define CONFIG_USB_EHCI
388
389#ifdef CONFIG_USB_EHCI
390#define CONFIG_CMD_USB
391#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
392#define CONFIG_USB_EHCI_FSL
393#define CONFIG_USB_STORAGE
394#define CONFIG_HAS_FSL_DR_USB
395#endif
396
397/*
398 * Environment Configuration
399 */
400
401#if defined(CONFIG_TSEC_ENET)
402#define CONFIG_HAS_ETH0
403#endif
404
405#define CONFIG_HOSTNAME BSC9131rdb
406#define CONFIG_ROOTPATH "/opt/nfsroot"
407#define CONFIG_BOOTFILE "uImage"
408#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
409
410#define CONFIG_BAUDRATE 115200
411
412#define CONFIG_EXTRA_ENV_SETTINGS \
413 "netdev=eth0\0" \
414 "uboot=" CONFIG_UBOOTPATH "\0" \
415 "loadaddr=1000000\0" \
416 "bootfile=uImage\0" \
417 "consoledev=ttyS0\0" \
418 "ramdiskaddr=2000000\0" \
419 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
420 "fdtaddr=c00000\0" \
421 "fdtfile=bsc9131rdb.dtb\0" \
422 "bdev=sda1\0" \
423 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
Priyanka Jain20732df2013-04-04 14:40:32 +0530424 "bootm_size=0x37000000\0" \
425 "othbootargs=ramdisk_size=600000 " \
426 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000427 "usbext2boot=setenv bootargs root=/dev/ram rw " \
428 "console=$consoledev,$baudrate $othbootargs; " \
429 "usb start;" \
430 "ext2load usb 0:4 $loadaddr $bootfile;" \
431 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
432 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
433 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
434
435#define CONFIG_RAMBOOTCOMMAND \
436 "setenv bootargs root=/dev/ram rw " \
437 "console=$consoledev,$baudrate $othbootargs; " \
438 "tftp $ramdiskaddr $ramdiskfile;" \
439 "tftp $loadaddr $bootfile;" \
440 "tftp $fdtaddr $fdtfile;" \
441 "bootm $loadaddr $ramdiskaddr $fdtaddr"
442
443#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
444
445#endif /* __CONFIG_H */