Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2017 NXP |
| 4 | * Copyright 2018 Emcraft Systems |
| 5 | * Copyright 2022 Purism |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #ifndef __LIBREM5_H |
| 10 | #define __LIBREM5_H |
| 11 | |
| 12 | /* #define DEBUG */ |
| 13 | |
| 14 | #include <version.h> |
| 15 | #include <linux/sizes.h> |
| 16 | #include <asm/arch/imx-regs.h> |
| 17 | |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 18 | #define CFG_SYS_FSL_USDHC_NUM 2 |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 19 | |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 20 | #define CONSOLE_ON_UART1 |
| 21 | |
| 22 | #ifdef CONSOLE_ON_UART1 |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 23 | #define CFG_MXC_UART_BASE UART1_BASE_ADDR |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 24 | #define CONSOLE_UART_CLK 0 |
| 25 | #define CONSOLE "ttymxc0" |
| 26 | #elif defined(CONSOLE_ON_UART2) |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 27 | #define CFG_MXC_UART_BASE UART2_BASE_ADDR |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 28 | #define CONSOLE_UART_CLK 1 |
| 29 | #define CONSOLE "ttymxc1" |
| 30 | #elif defined(CONSOLE_ON_UART3) |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 31 | #define CFG_MXC_UART_BASE UART3_BASE_ADDR |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 32 | #define CONSOLE_UART_CLK 2 |
| 33 | #define CONSOLE "ttymxc2" |
| 34 | #elif defined(CONSOLE_ON_UART4) |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 35 | #define CFG_MXC_UART_BASE UART4_BASE_ADDR |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 36 | #define CONSOLE_UART_CLK 3 |
| 37 | #define CONSOLE "ttymxc3" |
| 38 | #else |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 39 | #define CFG_MXC_UART_BASE UART1_BASE_ADDR |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 40 | #define CONSOLE_UART_CLK 0 |
| 41 | #define CONSOLE "ttymxc0" |
| 42 | #endif |
| 43 | |
| 44 | #ifndef CONFIG_SPL_BUILD |
| 45 | #define BOOT_TARGET_DEVICES(func) \ |
| 46 | func(MMC, mmc, 0) \ |
| 47 | func(USB, usb, 0) \ |
| 48 | func(DHCP, dhcp, na) |
| 49 | #include <config_distro_bootcmd.h> |
| 50 | #else |
| 51 | #define BOOTENV |
| 52 | #endif |
| 53 | |
| 54 | /* Initial environment variables */ |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 55 | #define CFG_EXTRA_ENV_SETTINGS \ |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 56 | "scriptaddr=0x80000000\0" \ |
| 57 | "pxefile_addr_r=0x80100000\0" \ |
| 58 | "kernel_addr_r=0x80800000\0" \ |
| 59 | "fdt_addr_r=0x84800000\0" \ |
| 60 | "ramdisk_addr_r=0x85000000\0" \ |
| 61 | "console=" CONSOLE ",115200\0" \ |
| 62 | "bootargs=u_boot_version=" PLAIN_VERSION "\0" \ |
| 63 | "stdin=usbacm,serial\0" \ |
| 64 | "stdout=usbacm,serial\0" \ |
| 65 | "stderr=usbacm,serial\0" \ |
| 66 | BOOTENV |
| 67 | |
| 68 | /* Link Definitions */ |
| 69 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 70 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 71 | #define CFG_SYS_INIT_RAM_SIZE 0x80000 |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 72 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 73 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 74 | #define PHYS_SDRAM 0x40000000 |
| 75 | #define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */ |
| 76 | |
| 77 | /* Monitor Command Prompt */ |
| 78 | |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 79 | #define CFG_SYS_FSL_ESDHC_ADDR 0 |
Angus Ainslie | 3f8667c | 2022-08-25 06:46:02 -0700 | [diff] [blame] | 80 | |
| 81 | #endif |