| Michal Simek | 4bc7734 | 2021-05-10 16:02:15 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for Xilinx ZynqMP Z2-VSOM |
| 4 | * |
| Michal Simek | 40d8349 | 2021-06-14 15:07:07 +0200 | [diff] [blame^] | 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. |
| Michal Simek | 4bc7734 | 2021-05-10 16:02:15 +0200 | [diff] [blame] | 6 | * |
| 7 | * Michal Simek <michal.simek@xilinx.com> |
| 8 | */ |
| 9 | |
| 10 | /* SD0 only supports 3.3V, no level shifter */ |
| 11 | &sdhci1 { /* FIXME - on CC - MIO 39 - 51 */ |
| 12 | status = "okay"; |
| 13 | no-1-8-v; |
| 14 | disable-wp; |
| 15 | broken-cd; |
| 16 | xlnx,mio-bank = <1>; |
| 17 | /* Do not run SD in HS mode from bootloader */ |
| 18 | sdhci-caps-mask = <0 0x200000>; |
| 19 | sdhci-caps = <0 0>; |
| 20 | max-frequency = <19000000>; |
| 21 | }; |