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git01.mediatek.com / filogic / uboot / 40d834931b4a8a0b48062740f216bf4681c619c6 / . / arch / arm / dts / zynqmp-sm-k26-revA.dts
blob: b613ab2342503d5ae1adba592e2a6d7eec6a45c2 [file] [log] [blame]
Michal Simek4bc77342021-05-10 16:02:15 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
4 *
Michal Simek40d83492021-06-14 15:07:07 +0200[diff] [blame^]5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
Michal Simek4bc77342021-05-10 16:02:15 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19 model = "ZynqMP SM-K26 Rev1/B/A";
20 compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
21 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
22 "xlnx,zynqmp";
23
24 aliases {
Michal Simek4bc77342021-05-10 16:02:15 +0200[diff] [blame]25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci0;
28 mmc1 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]29 nvmem0 = &eeprom;
30 nvmem1 = &eeprom_cc;
Michal Simek4bc77342021-05-10 16:02:15 +0200[diff] [blame]31 rtc0 = &rtc;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &dcc;
35 spi0 = &qspi;
36 spi1 = &spi0;
37 spi2 = &spi1;
38 usb0 = &usb0;
39 usb1 = &usb1;
Michal Simek4bc77342021-05-10 16:02:15 +0200[diff] [blame]40 };
41
42 chosen {
43 bootargs = "earlycon";
44 stdout-path = "serial1:115200n8";
45 };
46
47 memory@0 {
48 device_type = "memory"; /* 4GB */
49 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
50 };
51
52 gpio-keys {
53 compatible = "gpio-keys";
54 autorepeat;
55 fwuen {
56 label = "fwuen";
57 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
58 };
59 };
60
61 leds {
62 compatible = "gpio-leds";
63 ds35 {
64 label = "heartbeat";
65 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
66 linux,default-trigger = "heartbeat";
67 };
68
69 ds36 {
70 label = "vbus_det";
71 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
72 default-state = "on";
73 };
74 };
75
76 ams {
77 compatible = "iio-hwmon";
78 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
79 <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
80 <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
81 <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
82 <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
83 <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
84 <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
85 <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
86 <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
87 <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
88 };
89};
90
91&uart1 { /* MIO36/MIO37 */
92 status = "okay";
93};
94
95&qspi { /* MIO 0-5 - U143 */
96 status = "okay";
97 flash@0 { /* MT25QU512A */
98 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
99 #address-cells = <1>;
100 #size-cells = <1>;
101 reg = <0>;
102 spi-tx-bus-width = <1>;
103 spi-rx-bus-width = <4>;
104 spi-max-frequency = <40000000>; /* 40MHz */
105 partition@0 {
106 label = "Image Selector";
107 reg = <0x0 0x80000>; /* 512KB */
108 read-only;
109 lock;
110 };
111 partition@80000 {
112 label = "Image Selector Golden";
113 reg = <0x80000 0x80000>; /* 512KB */
114 read-only;
115 lock;
116 };
117 partition@100000 {
118 label = "Persistent Register";
119 reg = <0x100000 0x20000>; /* 128KB */
120 };
121 partition@120000 {
122 label = "Persistent Register Backup";
123 reg = <0x120000 0x20000>; /* 128KB */
124 };
125 partition@140000 {
126 label = "Open_1";
127 reg = <0x140000 0xC0000>; /* 768KB */
128 };
129 partition@200000 {
130 label = "Image A (FSBL, PMU, ATF, U-Boot)";
131 reg = <0x200000 0xD00000>; /* 13MB */
132 };
133 partition@f00000 {
134 label = "ImgSel Image A Catch";
135 reg = <0xF00000 0x80000>; /* 512KB */
136 read-only;
137 lock;
138 };
139 partition@f80000 {
140 label = "Image B (FSBL, PMU, ATF, U-Boot)";
141 reg = <0xF80000 0xD00000>; /* 13MB */
142 };
143 partition@1c80000 {
144 label = "ImgSel Image B Catch";
145 reg = <0x1C80000 0x80000>; /* 512KB */
146 read-only;
147 lock;
148 };
149 partition@1d00000 {
150 label = "Open_2";
151 reg = <0x1D00000 0x100000>; /* 1MB */
152 };
153 partition@1e00000 {
154 label = "Recovery Image";
155 reg = <0x1E00000 0x200000>; /* 2MB */
156 read-only;
157 lock;
158 };
159 partition@2000000 {
160 label = "Recovery Image Backup";
161 reg = <0x2000000 0x200000>; /* 2MB */
162 read-only;
163 lock;
164 };
165 partition@2200000 {
166 label = "U-Boot storage variables";
167 reg = <0x2200000 0x20000>; /* 128KB */
168 };
169 partition@2220000 {
170 label = "U-Boot storage variables backup";
171 reg = <0x2220000 0x20000>; /* 128KB */
172 };
173 partition@2240000 {
174 label = "SHA256";
175 reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
176 read-only;
177 lock;
178 };
179 partition@2250000 {
180 label = "User";
181 reg = <0x2250000 0x1db0000>; /* 29.5 MB */
182 };
183 };
184};
185
186&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/
187 status = "okay";
188 non-removable;
189 disable-wp;
190 bus-width = <8>;
191 xlnx,mio-bank = <0>;
192};
193
194&spi1 { /* MIO6, 9-11 */
195 status = "okay";
196 label = "TPM";
197 num-cs = <1>;
198 tpm@0 { /* slm9670 - U144 */
199 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
200 reg = <0>;
201 spi-max-frequency = <18500000>;
202 };
203};
204
205&i2c1 {
206 status = "okay";
207 clock-frequency = <400000>;
208 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
209 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
210
211 eeprom: eeprom@50 { /* u46 - also at address 0x58 */
212 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
213 reg = <0x50>;
214 /* WP pin EE_WP_EN connected to slg7x644092@68 */
215 };
216
217 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
218 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
219 reg = <0x51>;
220 };
221
222 /* da9062@30 - u170 - also at address 0x31 */
223 /* da9131@33 - u167 */
224 da9131: pmic@33 {
225 compatible = "dlg,da9131";
226 reg = <0x33>;
227 regulators {
228 da9131_buck1: buck1 {
229 regulator-name = "da9131_buck1";
230 regulator-boot-on;
231 regulator-always-on;
232 };
233 da9131_buck2: buck2 {
234 regulator-name = "da9131_buck2";
235 regulator-boot-on;
236 regulator-always-on;
237 };
238 };
239 };
240
241 /* da9130@32 - u166 */
242 da9130: pmic@32 {
243 compatible = "dlg,da9130";
244 reg = <0x32>;
245 regulators {
246 da9130_buck1: buck1 {
247 regulator-name = "da9130_buck1";
248 regulator-boot-on;
249 regulator-always-on;
250 };
251 };
252 };
253
254 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
255 /*
256 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
257 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
258 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
259 * With the FW fix, stdp4320 should respond to address 0x73 only.
260 */
261 /* slg7x644092@68 - u169 */
262 /* Also connected via JA1C as C23/C24 */
263};
264
265&gpio {
266 status = "okay";
267 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
268 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
269 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
270 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
271 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
272 "I2C1_SDA", "", "", "", "", /* 25 - 29 */
273 "", "", "", "", "", /* 30 - 34 */
274 "", "", "", "", "", /* 35 - 39 */
275 "", "", "", "", "", /* 40 - 44 */
276 "", "", "", "", "", /* 45 - 49 */
277 "", "", "", "", "", /* 50 - 54 */
278 "", "", "", "", "", /* 55 - 59 */
279 "", "", "", "", "", /* 60 - 64 */
280 "", "", "", "", "", /* 65 - 69 */
281 "", "", "", "", "", /* 70 - 74 */
282 "", "", "", /* 75 - 77, MIO end and EMIO start */
283 "", "", /* 78 - 79 */
284 "", "", "", "", "", /* 80 - 84 */
285 "", "", "", "", "", /* 85 - 89 */
286 "", "", "", "", "", /* 90 - 94 */
287 "", "", "", "", "", /* 95 - 99 */
288 "", "", "", "", "", /* 100 - 104 */
289 "", "", "", "", "", /* 105 - 109 */
290 "", "", "", "", "", /* 110 - 114 */
291 "", "", "", "", "", /* 115 - 119 */
292 "", "", "", "", "", /* 120 - 124 */
293 "", "", "", "", "", /* 125 - 129 */
294 "", "", "", "", "", /* 130 - 134 */
295 "", "", "", "", "", /* 135 - 139 */
296 "", "", "", "", "", /* 140 - 144 */
297 "", "", "", "", "", /* 145 - 149 */
298 "", "", "", "", "", /* 150 - 154 */
299 "", "", "", "", "", /* 155 - 159 */
300 "", "", "", "", "", /* 160 - 164 */
301 "", "", "", "", "", /* 165 - 169 */
302 "", "", "", ""; /* 170 - 174 */
303};
304
305&xilinx_ams {
306 status = "okay";
307};
308
309&ams_ps {
310 status = "okay";
311};
312
313&ams_pl {
314 status = "okay";
315};