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git01.mediatek.com / filogic / uboot / 409e2a11b94b9eabd80784c7858e2288a7e73905 / . / board / korat / init.S
blob: 20c5bddf6be2738f9e8bec272df4bd9ceb675898 [file] [log] [blame]
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]1/*
2 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]3 * SPDX-License-Identifier: GPL-2.0+
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]4 */
5
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]6#include <asm-offsets.h>
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]7#include <ppc_asm.tmpl>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]8#include <asm/mmu.h>
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]9#include <config.h>
10
11/**************************************************************************
12 * TLB TABLE
13 *
14 * This table is used by the cpu boot code to setup the initial tlb
15 * entries. Rather than make broad assumptions in the cpu source tree,
16 * this table lets each board set things up however they like.
17 *
18 * Pointer to the table is returned in r1
19 *
20 *************************************************************************/
21 .section .bootpg,"ax"
22 .globl tlbtab
23
24tlbtab:
25 tlbtab_start
26
27 /*
28 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
29 * speed up boot process. It is patched after relocation to enable SA_I
30 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]31 tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]32
33 /*
34 * TLB entries for SDRAM are not needed on this platform. They are
35 * generated dynamically in the SPD DDR2 detection routine.
36 */
37
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]38#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]39 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]40 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]41 AC_RWX | SA_G )
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]42#endif
43
44 /* TLB-entry for PCI Memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]45 tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]46 CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
Larry Johnson67682672008-03-17 11:10:35 -0500[diff] [blame]47
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]48 tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]49 CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
Larry Johnson67682672008-03-17 11:10:35 -0500[diff] [blame]50
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]51 tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]52 CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
Larry Johnson67682672008-03-17 11:10:35 -0500[diff] [blame]53
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]54 tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]55 CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]56
57 /* TLB-entry for EBC */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]58 tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]59
60 /* TLB-entry for Internal Registers & OCM */
61 /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]62 tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]63
64 /*TLB-entry PCI registers*/
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]65 tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]66
67 /* TLB-entry for peripherals */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]68 tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]69
70 /* TLB-entry PCI IO Space - from sr@denx.de */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]71 tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
Larry Johnson667a3d42007-12-27 11:28:51 -0500[diff] [blame]72
73 tlbtab_end
Larry Johnson67682672008-03-17 11:10:35 -0500[diff] [blame]74
75#if defined(CONFIG_KORAT_PERMANENT)
76 .globl korat_branch_absolute
77korat_branch_absolute:
78 mtlr r3
79 blr
80#endif